SLVSHR0 May 2025 TPS2HCS08-Q1
PRODUCTION DATA
To achieve optimal thermal performance, connect the exposed pad to a large copper pour. On the top PCB layer, the pour may extend beyond the package dimensions as shown in the layout examples below. In addition to this, it is recommended to have a VBB plane on one or more internal PCB layers and/or on the bottom layer. Vias should connect these planes to the top VBB pour.
TI recommends that the IO signals that connect to the microcontroller be routed to a via and then through an internal PCB layer.
The RSNS and CSNS components should be placed close to the SNS pin. If a ground network is used for reverse battery protection, the RSNS and CSNS should be connected from the SNS pin to the IC_GND net for accurate current sense measurements by the internal ADC.
If used in the design, CVBB1, should be placed as close as possible to the VBB and GND pin of the device. If a ground network is used for reverse battery protection, the CVBB1 capacitor should be connected from the VBB net to the IC_GND net.