The TPS2HCS08-Q1 communicates with the host controller through a high-speed SPI serial interface. The interface has three logic inputs: clock (CLK), chip select ( CS), serial data in (SDI), and one data out (SDO). The SDO is tri-stated when the CS pin is high. The maximum SPI clock rate is 8 MHz, but is limited in practice by the series protection resistor.

The device supports simple daisy chain SPI. This mode can be used with or without CRC.

The communication between the TPS2HCS08-Q1 IC and the controller or MCU is through a SPI bus in a primary-secondary configuration. The external MCU is always an SPI primary device that sends command requests on the SDI pin of the TPS2HCS08-Q1 IC and receives device responses on the SDO pin of the IC. The TPS2HCS08-Q1 device is always an SPI secondary device that receives command requests over the SDI line and sends responses (such as status and measured values) to the external MCU over the SDO line.

The TPS2HCS08-Q1 device can be connected to the primary MCU in the following formats:

Figure 8-6 Independent Secondary Configuration (Separate nCS Signal)

Figure 8-7 Daisy Chain Configuration

SPI Interface

The SPI interface pin behavior is described in this section

Chip Select ( CS or nCS)

The system microcontroller selects the TPS2HCS08-Q1 to receive communication using the  CS pin. With the  CS pin in a logic LOW state, command/configuration words may be sent to the TPS2HCS08-Q1 via the serial input (SDI) pin, and the device information can be retrieved by the microcontroller via the serial output (SDO) pin. The falling edge of the  CS enables the SDO output and latches the content of the GLOBAL_FAULT_TYPE register that will be sending out on SDO. The microcontroller may issue a READ command to retrieve information stored in the registers. The rising edge on the  CS pin initiates the following actions:

1. Addressed registers are updated if there is no SPI communication error and if it is an SPI write command.
2. Read clear register is cleared if a READ command to this register was issued during CS = LOW.

To avoid any corrupted data, it is essential the HIGH-to-LOW and LOW-to-HIGH transitions of the  CS signal occur only when SCLK is in a logic LOW state. A clean  CS signal is needed to ensure no incomplete SPI words are sent to the device. This pin is internally pulled up to the VDD rail.

System Clock

The system clock (SCLK) pin clocks the internal shift register of the TPS2HCS08-Q1. The SDI data is latched into the input shift register on the falling edge of the SCLK signal. The SDO pin shifts the device stored information out on the rising edge of SCLK. The SDO data is available for the microcontroller to read on the falling edge of SCLK.

False clocking of the shift register must be avoided to ensure validity of data and it is essential the SCLK pin be in a logic LOW state whenever  CS pin makes any transition. Therefore, it is recommended that the SCLK pin gets pulled to a logic LOW state as long as the device is not accessed and the  CS pin is at a logic HIGH state. When the  CS is in a logic HIGH state, any signal on the SCLK and SDI pins will be ignored and the SDO pin remains as a high impedance output.

Serial Data In (SDI) and Serial Data Out (SDO)

The SDI pin is used for serial instruction data input. SDI information is latched into the input shift register on the falling edge of the SCLK when  CS is low.

The SDO pin is the output from the internal shift register. This pin is internally pulled up to the VDD rail. SDO pin is high impedance when the  CS pin is high. Each successive rising SCLK edge makes the next data bit available for the microcontroller to read on the falling edge of SCLK. SDO will go back to high-impedance when  CS is high.

CRC Error Detection and Checking of Clocks

Setting the CRC_EN bit high enables CRC error detection. A CRC-4-ITU-Normal Check Sequence (FCS) is then sent along with each serial transaction. The 4-bit CRC is based on the normal generator polynomial X4+X+1 with CRC starting value = 1111. When CRC is enabled, the TPS2HCS08-Q1 expects a check byte appended to the SDI program/configure data that it receives.

SPI Frame Format

The device uses a 24-bit frame width (when CRC is not used) with the format as shown in Figure 8-8. Please note that the 16-bit wide "Data Out" in the SDO output is always for the previous SPI command frame (Read or Write).

Figure 8-8 24-bit Read, No CRC (CRC_EN=0)

Figure 8-9 24-bit Write, No CRC (CRC_EN=0)

Figure 8-10 32-bit Read, CRC Enabled (CRC_EN=1)

Figure 8-11 32-bit Write, CRC Enabled (CRC_EN=1)

GLOBAL_FAULT_TYPE [15:8] Bits

The TPS2HCS08-Q1 device, outputs the GLOBAL_FAULT_TYPE [15:8] bits on the SDO header so these status bits can be continously read thr during each SPI transaction. The GLOBAL_FAULT_TYPE [15:8] bits can be configured as read clear or real-time status bits based on the FLT_LTCH_DIS bit setting in the DEV_CONFIG register. The FLT_LTCH_DIS bit however does not apply to the LPM_STATUS bit.

If FLT_LTCH_DIS = 0, then the fault bits are latched and are cleared only when the associated regsiter in the bit description is read and the fault no longer exists. Table 8-3 below highlights which registers need to be read in order to clear each of the different fault bits if the fault no longer exists. This is also detailed in each of the bit descriptions in the register map.

If FLT_LTCH_DIS = 1, then the fault bits will not be latched and will clear when the fault no longer exists.

Figure 8-12 highlights the FLT_LTCH_DIS function of the device in regards to the GLOBAL_FAULT_TYPE [15:8] bits.

Figure 8-12 FLT_LTCH_DIS Implementation

SPI Watchdog Function

The TPS2HCS08-Q1 device offers an optional SPI watchdog function to monitor for valid SPI transactions from the host controller and loss of the VDD supply. If a valid SPI transaction does not occur in the configurable timeout period, WD_TO, then the FLT pin will go low and the WD_ERR bit in the GLOBAL_FAULT_TYPE register will be set to 1. A valid SPI transaction consists of a SPI transaction with no SPI errors and/or CRC errors (if enabled). If the VDD supply to the device drops below the VDD_UVLO threshold then SPI on the device is not operational. If the VDD supply remains below the VDD_UVLO for longer than the watchdog time period, then the device will issue a watchdog error where the WD_ERR bit will be set to 1 and the FLT pin will go low.

The watchdog function is enabled through WD_EN bit in the DEV_CONFIG register. Table 8-4 below showcases the different configurable watchdog timeout windows, WD_TO.

Depending on the version, the watchdog will work differently. See the below sections on how the watchdog works for TPS2HCS08A-Q1 and TPS2HCS08B-Q1.

SPI Watchdog Operation - TPS2HCS08A-Q1

If the watchdog function is enabled (WD_EN = 1) and a watchdog error occurs either do to no valid SPI transactions in the watchdog timeout window or due to a loss of VDD supply, WD_ERR = 1, FLT pin will go low, and the device will transition to the LIMP_HOME state where the output control of the channels will be set by the CHx_LH_IN bits in the DEV_CONFIG register. Note, the LIMPHOME_STAT bit will not be set to 1 as a result of watchdog error. Once a valid SPI transaction has been detected, the FLT pin will go high and the device will automatically exit the LIMP_HOME state and will revert the output control of the channel back to the CHx_ON bit. The WD_ERR bit in the GLOBAL_FAULT_TYPE register will be latched to 1 as a result of a SPI watchdog timeout error and will be cleared only after read and the error no longer exists.

SPI watchdog Operation - TPS2HCS08B-Q1

If the watchdog function is enabled (WD_EN = 1) and a watchdog error occurs either do to no valid SPI transactions in the watchdog timeout window or due to a loss of VDD supply, WD_ERR = 1 and the FLT pin will go low. The output state will not change as result of the watchdog error and the output control of the channels will continue to follow the DIx exclusively. Once a valid SPI transaction has been detected, the FLT pin will go high. The WD_ERR bit in the GLOBAL_FAULT_TYPE register will be latched to 1 as a result of a SPI watchdog timeout error and will be cleared only after read and the error no longer exists.