SLVSHR0 May 2025 TPS2HCS08-Q1
PRODUCTION DATA
When the PARALLEL_12 bit is set to 1, the device supports a parallel mode where the outputs of the device can be connected together externally to operate the device as a single channel device. This reduces the RON approximately by half and increases the continuous output current by approximately 2x.
When setting the PARALLEL_12 bit, both channels must be off in order for it to take effect. To confirm if the PARALLEL_12 bit has taken effect, the DEV_CONFIG register can be read to verify the PARALLEL_12 bit is set to 1.
The following sections cover the different configurations and behaviors specific to the parallel mode of the device. If any function or feature is not described in the followings sections, the device will operate the same as in single channel operation for that function or feature.
In parallel mode, channel control in the ACTIVE state is set only through the CH1_ON bit in the SW_STATE register for TPS2HCS08A-Q1. For TPS2HCS08B-Q1, channel control in ACTIVE state is set only through the DI1 pin. For LIMP_HOME state, channel control is set only through CH1_LH_IN bits only in the DEV_CONFIG register.
In parallel mode, if a fault on either or both channels, the fault flags for both channels will assert for the respective fault.
In parallel mode, the ADC diagnostics (ISNS, VSNS, VBBSNS, VDS_SNS, and TSNS) are available for both channels. These diagnostics can be enabled or disabled on a per channel basis through the respective CHx_CONFIG registers.
To enter KSNS2 operation (or also known as OL_ON_EN_CHx = 1 mode), the output current must be below 2x IENTRY_OL_ON before the OL_ON_EN_CH1 bit is set to 1. If the current is not below 2x IENTRY_OL_ON, the KSNS2 operation will not be entered and the KSNS1 operation will still be active. If the channel is operating with KSNS2 and the output current increases above 2x IEXIT_OL_ON, the device will automatically transition out of KSNS2 to KSNS1 where the OL_ON_EN_CH1 bit will be reset to 0 and the full MOSFET is active. If the current falls below 2x IENTRY_OL_ON again then the OL_ON_EN_CH1 bit needs to be set back to 1 to transition to KSNS2 operation again. The system can manually exit KSNS2 operation by writing OL_ON_EN_CH1 = 0. When measuring the output current through the integrated ADC in KSNS2 operation, the system should continue to monitor the OL_ON_EN_CH1 = 1 bit to ensure the device is still in KSNS2 operation when the output current measurement is read.
Off state open load detection and off state short to battery detection settings are set by the CH1_CONFIG register only. The device will only enable the circuitry on channel 1 to detect off state open load and the off state short to battery.
In parallel mode, the overcurrent protection in the optional inrush period is set by the ILIM_CONFIG_CH1 register only. Either of the two capacitive charging modes, no capacitive charging or current regulation, can be used in parallel mode and is set by the CAP_CHRG_CH1 bits. The duration for the inrush period is set by INRUSH_DURATION_CH1. The value for the capacitive charging is set by the INRUSH_LIMIT_CH1 bits and the effective value for the entire device for parallel operation will be approximately double the INRUSH_LIMIT_CH1 setting.
The overcurrent protection and thermal shutdown protection in both channels will be enabled for the two capacitive charging modes. For the no capacitive charging mode, if the output current through either channel goes above the INRUSH_LIMIT_CH1 setting then both channels will be turned off. For both capacitive charging modes, if either channel has a thermal shutdown fault, both channels will be turned off.
See Table 8-12below for more details on how the device can be configured for the overcurrent protection in the optional inrush period.
| Capacitive Charging Mode (CAP_CHRG_CH1) | Duration Set By | Value Set By | Effective Typical Value When PARALLEL_12 = 1 |
|---|---|---|---|
| 00 | INRUSH_DURATION_CH1 [2:0] | INRUSH_LIMIT_CH1 [3:0] | 2x INRUSH_LIMIT_CH1 [3:0] |
| 10 | INRUSH_DURATION_CH1 [2:0] | INRUSH_LIMIT_CH1 [3:0] | 2x INRUSH_LIMIT_CH1 [3:0] |
In parallel mode, the immediate shutdown overcurrent protection (IOCP) in the steady state operation is set by the ILIMIT_SET_CH1 bits in the ILIM_CONFIG_CH1 register only. The effective value for the entire device for parallel operation will be approximately double the ILIMIT_SET_CH1 setting.
The overcurrent protection and thermal shutdown protection in both channels will be enabled in steady state operation. If the output current through either channel goes above the ILIMIT_SET_CH1 setting then both channels will be turned off.
The max ILIMIT_SET_CH1 value that is supported for parallel mode is 40A. If CAP_CHRG_CH1 = 00, the max INRUSH_LIMIT_CH1 value that is supported for parallel mode is 40A.
In parallel mode, the I2T protection is set by the I2T_CONFIG_CH1 register only. The value for INOM for the I2T is set by the NOM_CUR_CH1 bits and the effective value for the entire device for parallel operation will be approximately double the NOM_CUR_CH1 setting. The value for the I2T threshold is set by the I2T_TRIP_CH1 bits and the effective value for the entire device for the parallel operation is approximately quadruple the I2T_TRIP_CH1 setting. The value for the ISWCL is set by the ISWCL_CH1 bits and the effective value for the entire device for the parallel operation is approximately double the ISWCL_CH1 setting.
Enabling of I2T in parallel mode is done only through the I2T_EN_CH1 bit in the ILIM_CONFIG_CH1 register.
For I2T accumulation, only the current sense for channel 1 is used. If the I2T_TRIP_CH1 value is exceeded for channel 1 then both channels will be turned off.
In parallel mode, the MANUAL_LPM is entered through the MANUAL_LPM_ENTRY bit. The device operates the same as in single channel operation as described in the MANUAL_LPM section with the following exceptions:
In parallel mode, the AUTO_LPM is entered AUTO_LPM_ENTRY bit is set to 1. The device operates the same as in single channel operation as described in the AUTO_LPM section with the following exceptions:
In parallel mode, the PWM settings will be set by the PWM_CH1 register only. The PWM_SHIFT_DIS bit will be ignored as both channels will turn on at the same time. Enabling of PWM for parallel mode is done through the PWM_EN_CH1 bit.
The RON for each channel varies slightly from each other and can cause a small load mismatch. This is specified in the electrical characteristics through the ΔRON parameter.
In parallel mode, the routing of the output channels is important to avoid any additional load mismatch. The output traces should be symmetrical to avoid any extra resistance which can cause uneven current draw through the output channels.