SLVSHR0 May 2025 TPS2HCS08-Q1
PRODUCTION DATA
The device provides enhanced fault reporting through a FLT status pin and fault status bits through SPI.
The FLT status pin allows the device to interrupt the system when a fault has occurred on the device. The FLT status pin is an open drain output that asserts low when a fault occurs on the device. For faults which are read clear, the FLT pin will go high if the fault no longer exists and the specific register to clear the fault is read. Indication on the FLT pin can be masked for some faults through FAULT_MASK register. See the FAULT_MASK register for more details.
The device also provides fault information through SPI through a global fault register (GLOBAL_FAULT_TYPE) and channel specific fault registers (FLT_STAT_CHx) to enable the system to quickly diagnose what caused the fault in the device. The device outputs the GLOBAL_FAULT_TYPE [15:8] bits on the SDO header so these status bits can be continosly read for each SPI transaction.
For more details on each of the individual fault status bits see the GLOBAL_FAULT_TYPE and FLT_STAT_CHx registers in the register map.
Table 8-5 highlights how the device signals different events through the FLT pin and the fault status bits.
When the device is in low power mode no fault information is available through the FLT pin. If short circuit were to occur in LPM the device would protect itself then transition to ACTIVE state and then will signal fault on the FLT pin and in the fault status registers.
| Event / Fault | Detection | Protection | GLOBAL_FAULT_TYPE reporting | FLT_STAT_CHx reporting | FLT indication | |
|---|---|---|---|---|---|---|
| FET - Overtemperature Warning | Y | N | CHx_FLT1 | THERMAL_WRN_CHx1 | N | |
| FET - Temperature shutdown (TSD) | Y | Y | CHx_FLT1 and CHAN_OCP_I2T_TSD1 | THERMAL_WRN_CHx1 | Y | |
| IOCP - Immediate shutdown | Y | Y | CHx_FLT1 and CHAN_OCP_I2T_TSD1 | ILIMIT_CHx1 | Y | |
| ICL_REG - Current limit regulation | Y | Y | N/A | N/A | N | |
| ICL_REG - Current limit regulation - inrush period expiry | Y | Y | CHx_FLT1 and CHAN_OCP_I2T_TSD1 | ILIMIT_CHx1 | Y | |
| ICL_REG - Current limit regulation - TSD | Y | Y | CHx_FLT1 and CHAN_OCP_I2T_TSD1 | ILIMIT_CHx1 and THERMAL_SD_CHx1 | Y | |
| Channel in TRETRY
(LATCH_CHx = 0) |
Y | N/A | N/A | FLT_CHx | Y | |
| Channel is latched-off (LATCH_CHx = 1) |
Y | N/A | N/A | LATCH_STAT_CHx and FLT_CHx | Y | |
| Limp Home Entry (LHI = 1) | Y | N/A | GLOBAL_ERR_WRN1 and LIMPHOME_STAT2 | N/A | N | |
| Active I2T Accumulation or Decrement | Y | N/A | N/A | I2T_MOD_CHx | N | |
| I2T Shutdown | Y | Y | CHx_FLT1 and CHAN_OCP_I2T_TSD1 | I2T_FLT_CHx1 and FLT_CHx | Y | |
| VOUT shorted to VBB | Y | N |
CHx_FLT1 and OL_SHRT_VBB_OFF_FLT1 (if OL_SVBB_EN_CHx = 01) |
OL_OFF_CHx1 (if OL_SVBB_EN_CHx = 01) |
Y, unless masked | |
| Open load | Off State | Y | N |
CHx_FLT1 and OL_SHRT_VBB_OFF_FLT1 (if OL_SVBB_EN_CHx=10) |
OL_OFF_CHx1 (if OL_SVBB_EN_CHx=10) |
Y, unless masked |
| On State | Y | N | N/A | N/A | N | |
| Reverse battery | Y | Y, with external components | N/A | N/A | N | |
| VBB UV warning | Y | N | GLOBAL_ERR_WRN1 and VBB_UV_WRN1 | N/A | N | |
| VBB_UVLO | Y | Y | GLOBAL_ERR_WRN1 and VBB_UVLO1 | N/A | Y | |
| VDD_UVLO | Y | Y | GLOBAL_ERR_WRN1 and VDD_UVLO1 | N/A | N | |
| Power on Reset (POR) | Y | Y | GLOBAL_ERR_WRN1 and POR1 | N/A | Y | |
| Loss of GND | Y | Y, with RSDO ≥ 768? | N/A | N/A | N | |
| SPI Watchdog Error | Y | N/A | GLOBAL_ERR_WRN1 and WD_ERR1 (if WD_EN = 1) | N/A | Y, unless masked | |
| SPI Frame Error | Y | N/A | GLOBAL_ERR_WRN1 and SPI_ERR1 | N/A | Y, unless masked | |
| SPI CRC Error | Y | N/A | GLOBAL_ERR_WRN1 and SPI_ERR1 (if CRC_EN = 1) | N/A | Y, unless masked | |