SLVSHR0 May 2025 TPS2HCS08-Q1
PRODUCTION DATA
Control of the eFuse channels varies depending on the device version. See the below sections for more details on the ouptut control method for each of the device versions.
The state of the eFuse outputs for ACTIVE state for TPS2HCS08A-Q1 is controlled by the CHx_ON bits in the SW_STATE register. Table 8-1 below showcases the output control method in each state for the TPS2HCS08A-Q1 device.
| State | Control Type | Output Control Description |
|---|---|---|
| SLEEP | N/A | Output OFF |
| CONFIG | SPI | Output OFF |
| ACTIVE | SPI | Set by CHx_ON |
| LIMP_HOME |
SPI or DI pin |
Set by SPI through CHx_LH_IN bit See Section 8.3.7 section for more details on output control settings |
| AUTO_LPM | SPI | Set by CHx_ON prior to AUTO_LPM entry |
| MANUAL_LPM | SPI | Set by CHx_ON prior to MANUAL_LPM entry |
| VBB_WRN | SPI | Set by CHx_ON |
| VBB_UVLO | N/A | Output OFF |
The state of the eFuse outputs for ACTIVE state for TPS2HCS08B-Q1 is controlled exclusively by the DI1 for channel 1 and DI2 for channel 2. The CHx_ON bits in the SW_STATE register have no effect on the output state of the TPS2HCS08B-Q1. Table 8-2 below showcases the output control method in each state for the TPS2HCS08B-Q1 device.
| State | Control Type | Output Control Description |
|---|---|---|
| SLEEP | N/A | Output OFF |
| CONFIG | DIx | Output OFF |
| ACTIVE | DIx | Set by DIx pins |
| AUTO_LPM | DIx | Set by DIx pins prior to AUTO_LPM entry |
| MANUAL_LPM | DIx | Set by DIx pins prior to MANUAL_LPM entry |
| VBB_WRN | DIx | Set by DIx pins |
| VBB_UVLO | N/A | Output OFF |