The features of the Arm Cortex-R5F CPU include:
- An integer unit with integral
Embedded ICE-RT logic.
- High-speed Advanced
Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI)
for Level two (L2) master and slave interfaces.
- Floating-Point
Coprocessor
- Dynamic branch prediction
with a global history buffer, and a 4-entry return stack
- Low interrupt latency.
- Nonmaskable interrupt.
- Harvard Level one (L1) memory
system with:
- 32KB of instruction
cache and 32KB of data cache implemented . Both Instruction and data cache have ECC
support.
- ARMv7-R architecture
Memory Protection Unit (MPU) with 16 regions
- Dual core logic for fault
detection in safety-critical applications.
- L2 memory interface:
- Single 64-bit master
AXI interface
- 64-bit slave AXI
interface to cache memories
- 32-bit AXI_Peri ports
to support low latency peripheral ports
- Debug interface to a
CoreSight Debug Access Port (DAP).
- Performance Monitoring Unit
(PMU).
- Vectored Interrupt Controller
(VIC) port.
- AXI accelerator coherency
port (ACP) supporting IO coherency with write-through cacheable regions
- Ability to generate ECC on L2
data buses and parity of all control channels
- Both CPU cores in
lock-step
- Eight hardware breakpoints
- Eight watchpoints