ZHCSV76A June 2022 – March 2024 TMS570LC4357-SEP
PRODUCTION DATA
Figure 8-30 RMII Timing Diagram| NO. | MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|---|
| 1 | tc(REFCLK) | Cycle time, RMII_REFCLK | 20 | ns | ||
| 2 | tw(REFCLKH) | Pulse width, RMII_REFCLK high | 7 | 13 | ns | |
| 3 | tw(REFCLKL) | Pulse width, RMII_REFCLK low | 7 | 13 | ns | |
| 6 | tsu(RXD-REFCLK) | Input setup time, RMII_RXD[1:0] valid before RMII_REFCLK high | 4 | ns | ||
| 7 | th(REFCLK-RXD) | Input hold time, RMII_RXD[1:0] valid after RMII_REFCLK high | 2 | ns | ||
| 8 | tsu(CRSDV-REFCLK) | Input setup time, RMII_CRS_DV valid before RMII_REFCLK high | 4 | ns | ||
| 9 | th(REFCLK-CRSDV) | Input hold time, RMII_CRS_DV valid after RMII_REFCLK high | 2 | ns | ||
| 10 | tsu(RXER-REFCLK) | Input setup time, RMII_RX_ER valid before RMII_REFCLK high | 4 | ns | ||
| 11 | th(REFCLK-RXER) | Input hold time, RMII_RX_ER valid after RMII_REFCLK high | 2 | ns | ||
| NO. | PARAMETER | MIN | MAX | UNIT | |
|---|---|---|---|---|---|
| 4 | td(REFCLK-TXD) | Output delay time, RMII_REFCLK high to RMII_TXD[1:0] invalid | 2 | ns | |
| Output delay time, RMII_REFCLK high to RMII_TXD[1:0] valid | 16 | ns | |||
| 5 | td(REFCLK-TXEN) | Output delay time, RMII_REFCLK high to RMII_TXEN invalid | 2 | ns | |
| Output delay time, RMII_REFCLK high to RMII_TXEN valid | 16 | ns | |||