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ZHCSV76A June 2022 – March 2024 TMS570LC4357-SEP

PRODUCTION DATA

封裝選項

請參考 PDF 數據表獲取器件具體的封裝圖。

機械數據 (封裝 | 引腳)

GWT|337

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

zhcsv76a_oa

8.12.5 SPI Slave Mode I/O Timings

Table 8-40 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO = input, and SPISOMI = output)⁽¹⁾⁽²⁾⁽³⁾⁽⁴⁾

NO.	Parameter		MIN	MAX	Unit
1	t_c(SPC)S	Cycle time, SPICLK⁽⁵⁾	40		ns
2⁽⁶⁾	t_w(SPCH)S	Pulse duration, SPICLK high (clock polarity = 0)	14		ns
2⁽⁶⁾	t_w(SPCL)S	Pulse duration, SPICLK low (clock polarity = 1)	14		ns
3⁽⁶⁾	t_w(SPCL)S	Pulse duration, SPICLK low (clock polarity = 0)	14		ns
3⁽⁶⁾	t_w(SPCH)S	Pulse duration, SPICLK high (clock polarity = 1)	14		ns
4⁽⁶⁾	t_{d(SPCH-SOMI)S}	Delay time, SPISOMI valid after SPICLK high (clock polarity = 0)		t_rf(SOMI) + 20	ns
4⁽⁶⁾	t_{d(SPCL-SOMI)S}	Delay time, SPISOMI valid after SPICLK low (clock polarity = 1)		t_rf(SOMI) + 20	ns
5⁽⁶⁾	t_{h(SPCH-SOMI)S}	Hold time, SPISOMI data valid after SPICLK high (clock polarity =0)	2		ns
5⁽⁶⁾	t_{h(SPCL-SOMI)S}	Hold time, SPISOMI data valid after SPICLK low (clock polarity =1)	2		ns
6⁽⁶⁾	t_{su(SIMO-SPCL)S}	Setup time, SPISIMO before SPICLK low (clock polarity = 0)	4		ns
6⁽⁶⁾	t_{su(SIMO-SPCH)S}	Setup time, SPISIMO before SPICLK high (clock polarity = 1)	4		ns
7⁽⁶⁾	t_{h(SPCL-SIMO)S}	Hold time, SPISIMO data valid after SPICLK low (clock polarity = 0)	2		ns
7⁽⁶⁾	t_{h(SPCH-SIMO)S}	Hold time, SPISIMO data valid after S PICLK high (clock polarity = 1)	2		ns
8	t_{d(SPCL-SENAH)S}	Delay time, SPIENAn high after last SPICLK low (clock polarity = 0)	1.5t_c(VCLK)	2.5t_c(VCLK)+t_r(ENAn)+ 22	ns
8	t_{d(SPCH-SENAH)S}	Delay time, SPIENAn high after last SPICLK high (clock polarity = 1)	1.5t_c(VCLK)	2.5t_c(VCLK)+ t_r(ENAn) + 22	ns
9	t_{d(SCSL-SENAL)S}	Delay time, SPIENAn low after SPICSn low (if new data has been written to the SPI buffer)	t_f(ENAn)	t_c(VCLK)+t_f(ENAn)+27	ns

(1) The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is cleared.

(2) If the SPI is in slave mode, the following must be true: t_c(SPC)S ≥ (PS + 1) t_c(VCLK), where PS = prescale value set in SPIFMTx.[15:8].

(3) For rise and fall timings, see Table 6-6, Switching Characteristics for Output Timings versus Load Capacitance (LC).

(4) t_c(VCLK) = interface clock cycle time = 1 /f_(VCLK)

(5) When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: t_c(SPC)S ≥ (PS +1)t_c(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: t_c(SPC)S = 2t_c(VCLK) ≥ 40ns.

(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

Figure 8-24 SPI Slave Mode External Timing (CLOCK PHASE = 0)

Figure 8-25 SPI Slave Mode Enable Timing (CLOCK PHASE = 0)

Table 8-41 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO = input, and SPISOMI = output)⁽¹⁾⁽²⁾⁽³⁾⁽⁴⁾

NO.	Parameter		MIN	MAX	Unit
1	t_c(SPC)S	Cycle time, SPICLK⁽⁵⁾	40		ns
2⁽⁶⁾	t_w(SPCH)S	Pulse duration, SPICLK high (clock polarity = 0)	14		ns
2⁽⁶⁾	t_w(SPCL)S	Pulse duration, SPICLK low (clock polarity = 1)	14		ns
3⁽⁶⁾	t_w(SPCL)S	Pulse duration, SPICLK low (clock polarity = 0)	14		ns
3⁽⁶⁾	t_w(SPCH)S	Pulse duration, SPICLK high (clock polarity = 1)	14		ns
4⁽⁶⁾	t_{d(SOMI-SPCL)S}	Dealy time, SPISOMI data valid after SPICLK low (clock polarity = 0)		t_rf(SOMI) + 20	ns
4⁽⁶⁾	t_{d(SOMI-SPCH)S}	Delay time, SPISOMI data valid after SPICLK high (clock polarity = 1)		t_rf(SOMI) + 20	ns
5⁽⁶⁾	t_{h(SPCL-SOMI)S}	Hold time, SPISOMI data valid after SPICLK high (clock polarity =0)	2		ns
5⁽⁶⁾	t_{h(SPCH-SOMI)S}	Hold time, SPISOMI data valid after SPICLK low (clock polarity =1)	2		ns
6⁽⁶⁾	t_{su(SIMO-SPCH)S}	Setup time, SPISIMO before SPICLK high (clock polarity = 0)	4		ns
6⁽⁶⁾	t_{su(SIMO-SPCL)S}	Setup time, SPISIMO before SPICLK low (clock polarity = 1)	4		ns
7⁽⁶⁾	t_{v(SPCH-SIMO)S}	High time, SPISIMO data valid after SPICLK high (clock polarity = 0)	2		ns
7⁽⁶⁾	t_{v(SPCL-SIMO)S}	High time, SPISIMO data valid after SPICLK low (clock polarity = 1)	2		ns
8	t_{d(SPCH-SENAH)S}	Delay time, SPIENAn high after last SPICLK high (clock polarity = 0)	1.5t_c(VCLK)	2.5t_c(VCLK)+t_r(ENAn) + 22	ns
8	t_{d(SPCL-SENAH)S}	Delay time, SPIENAn high after last SPICLK low (clock polarity = 1)	1.5t_c(VCLK)	2.5t_c(VCLK)+t_r(ENAn) + 22	ns
9	t_{d(SCSL-SENAL)S}	Delay time, SPIENAn low after SPICSn low (if new data has been written to the SPI buffer)	t_f(ENAn)	t_c(VCLK)+t_f(ENAn)+ 27	ns
10	t_{d(SCSL-SOMI)S}	Delay time, SOMI valid after SPICSn low (if new data has been written to the SPI buffer)	t_c(VCLK)	2t_c(VCLK)+t_rf(SOMI)+ 28	ns

(1) The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is set.

(2) If the SPI is in slave mode, the following must be true: tc(SPC)S ≤ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].

(3) For rise and fall timings, see Table 6-6, Switching Characteristics for Output Timings versus Load Capacitance (LC).

(4) t_c(VCLK) = interface clock cycle time = 1 /f_(VCLK)

(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

Figure 8-26 SPI Slave Mode External Timing (CLOCK PHASE = 1)

Figure 8-27 SPI Slave Mode Enable Timing (CLOCK PHASE = 1)