ZHCSV76A June 2022 – March 2024 TMS570LC4357-SEP
PRODUCTION DATA
| NO. | MIN(1) | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|---|
| Reads and Writes | ||||||
| 2 | tw(EM_WAIT) | Pulse duration, EMIFnWAIT assertion and deassertion | 2E | ns | ||
| Reads | ||||||
| 12 | tsu(EMDV-EMOEH) | Setup time, EMIFDATA[15:0] valid before EMIFnOE high | 11 | ns | ||
| 13 | th(EMOEH-EMDIV) | Hold time, EMIFDATA[15:0] valid after EMIFnOE high | 0.5 | ns | ||
| 14 | tsu(EMOEL-EMWAIT) | Setup Time, EMIFnWAIT asserted before end of Strobe Phase(2) | 4E+14 | ns | ||
| Writes | ||||||
| 28 | tsu(EMWEL-EMWAIT) | Setup Time, EMIFnWAIT asserted before end of Strobe Phase(2) | 4E+14 | ns | ||
| NO. | PARAMETER(1)(2)(3) | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| Reads and Writes | ||||||
| 1 | td(TURNAROUND) | Turn around time | (TA)*E -3 | (TA)*E | (TA)*E + 3 | ns |
| Reads | ||||||
| 3 | tc(EMRCYCLE) | EMIF read cycle time (EW = 0) | (RS+RST+RH)*E-3 | (RS+RST+RH)*E | (RS+RST+RH)*E + 3 | ns |
| EMIF read cycle time (EW = 1) | (RS+RST+RH+ EWC)*E -3 | (RS+RST+RH+ EWC)*E | (RS+RST+RH+ EWC)*E + 3 | ns | ||
| 4 | tsu(EMCEL-EMOEL) | Output setup time, EMIF_nCS[4:2] low to EMIF_nOE low (SS = 0) | (RS)*E-3 | (RS)*E | (RS)*E+3 | ns |
| Output setup time, EMIFnCS[4:2] low to EMIF_nOE low (SS = 1) | –3 | 0 | 3 | ns | ||
| 5 | th(EMOEH-EMCEH) | Output hold time, EMIF_nOE high to EMIF_nCS[4:2] high (SS = 0) | (RH)*E -4 | (RH)*E | (RH)*E + 3 | ns |
| Output hold time, EMIF_nOE high to EMIF_nCS[4:2] high (SS = 1) | –4 | 0 | 3 | ns | ||
| 6 | tsu(EMBAV-EMOEL) | Output setup time, EMIF_BA[1:0] valid to EMIF_nOE low | (RS)*E-3 | (RS)*E | (RS)*E+3 | ns |
| 7 | th(EMOEH-EMBAIV) | Output hold time, EMIF_nOE high to EMIF_BA[1:0] invalid | (RH)*E-4 | (RH)*E | (RH)*E+3 | ns |
| 8 | tsu(EMBAV-EMOEL) | Output setup time, EMIF_ADDR[21:0] valid to EMIF_nOE low | (RS)*E-3 | (RS)*E | (RS)*E+3 | ns |
| 9 | th(EMOEH-EMAIV) | Output hold time, EMIF_nOE high to EMIF_ADDR[21:0] invalid | (RH)*E-4 | (RH)*E | (RH)*E+3 | ns |
| 10 | tw(EMOEL) | EMIF_nOE active low width (EW = 0) | (RST)*E-3 | (RST)*E | (RST)*E+3 | ns |
| EMIF_nOE active low width (EW = 1) | (RST+EWC) *E-3 | (RST+EWC)*E | (RST+EWC) *E+3 | ns | ||
| 11 | td(EMWAITH-EMOEH) | Delay time from EMIF_nWAIT deasserted to EMIF_nOE high | 3E-3 | 4E | 4E+5 | ns |
| 29 | tsu(EMDQMV-EMOEL) | Output setup time, EMIF_nDQM[1:0] valid to EMIF_nOE low | (RS)*E-5 | (RS)*E | (RS)*E+3 | ns |
| 30 | th(EMOEH-EMDQMIV) | Output hold time, EMIF_nOE high to EMIF_nDQM[1:0] invalid | (RH)*E-4 | (RH)*E | (RH)*E+5 | ns |
| Writes | ||||||
| 15 | tc(EMWCYCLE) | EMIF write cycle time (EW = 0) | (WS+WST+WH)* E-3 | (WS+WST+WH)*E | (WS+WST+WH)* E+3 | ns |
| EMIF write cycle time (EW = 1) | (WS+WST+WH+ EWC)*E -3 | (WS+WST+WH+ EWC)*E | (WS+WST+WH+ EWC)*E + 3 | ns | ||
| 16 | tsu(EMCEL-EMWEL) | Output setup time, EMIF_nCS[4:2] low to EMIF_nWE low (SS = 0) | (WS)*E -3 | (WS)*E | (WS)*E + 3 | ns |
| Output setup time, EMIF_nCS[4:2] low to EMIF_nWE low (SS = 1) | –3 | 0 | 3 | ns | ||
| 17 | th(EMWEH-EMCEH) | Output hold time, EMIF_nWE high to EMIF_nCS[4:2] high (SS = 0) | (WH)*E-3 | (WH)*E | (WH)*E+3 | ns |
| Output hold time, EMIF_nWE high to EMIF_CS[4:2] high (SS = 1) | –3 | 0 | 3 | ns | ||
| 18 | tsu(EMDQMV-EMWEL) | Output setup time, EMIF_nDQM[1:0] valid to EMIF_nWE low | (WS)*E-3 | (WS)*E | (WS)*E+3 | ns |
| 19 | th(EMWEH-EMDQMIV) | Output hold time, EMIF_nWE high to EMIF_nDQM[1:0] invalid | (WH)*E-3 | (WH)*E | (WH)*E+3 | ns |
| 20 | tsu(EMBAV-EMWEL) | Output setup time, EMIF_BA[1:0] valid to EMIF_nWE low | (WS)*E-3 | (WS)*E | (WS)*E+3 | ns |
| 21 | th(EMWEH-EMBAIV) | Output hold time, EMIF_nWE high to EMIF_BA[1:0] invalid | (WH)*E-3 | (WH)*E | (WH)*E+3 | ns |
| 22 | tsu(EMAV-EMWEL) | Output setup time, EMIF_ADDR[21:0] valid to EMIF_nWE low | (WS)*E-3 | (WS)*E | (WS)*E+3 | ns |
| 23 | th(EMWEH-EMAIV) | Output hold time, EMIF_nWE high to EMIF_ADDR[21:0] invalid | (WH)*E-3 | (WH)*E | (WH)*E+3 | ns |
| 24 | tw(EMWEL) | EMIF_nWE active low width (EW = 0) | (WST)*E-3 | (WST)*E | (WST)*E+3 | ns |
| EMIF_nWE active low width (EW = 1) | (WST+EWC) *E-3 | (WST+EWC)*E | (WST+EWC) *E+3 | ns | ||
| 25 | td(EMWAITH-EMWEH) | Delay time from EMIF_nWAIT deasserted to EMIF_nWE high | 3E+3 | 4E | 4E+14 | ns |
| 26 | tsu(EMDV-EMWEL) | Output setup time, EMIF_DATA[15:0] valid to EMIF_nWE low | (WS)*E-3 | (WS)*E | (WS)*E+3 | ns |
| 27 | th(EMWEH-EMDIV) | Output hold time, EMIF_nWE high to EMIF_DATA[15:0] invalid | (WH)*E-3 | (WH)*E | (WH)*E+3 | ns |