SPRS814D March 2012 – October 2019 TMS320C6655 , TMS320C6657
PRODUCTION DATA.
請參考 PDF 數據表獲取器件具體的封裝圖。
| NO. | MIN | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| 1 | tc(INCLK) | Cycle time, CHn_CLK | SDR mode | 13.33 | ns | |
| DDR mode | 26.66 | |||||
| 2 | tw(INCLKH) | Pulse width, CHn_CLK high | SDR mode | 5 | ns | |
| DDR mode | 10 | |||||
| 3 | tw(INCLKL) | Pulse width, CHn_CLK low | SDR mode | 5 | ns | |
| DDR mode | 10 | |||||
| 4 | tsu(STV-INCLKH) | Setup time, CHn_START valid before CHn_CLK high | 4 | ns | ||
| 5 | th(INCLKH-STV) | Hold time, CHn_START valid after CHn_CLK high | 0.8 | ns | ||
| 6 | tsu(ENV-INCLKH) | Setup time, CHn_ENABLE valid before CHn_CLK high | 4 | ns | ||
| 7 | th(INCLKH-ENV) | Hold time, CHn_ENABLE valid after CHn_CLK high | 0.8 | ns | ||
| 8 | tsu(DV-INCLKH) | Setup time, CHn_DATA/XDATA valid before CHn_CLK high | 4 | ns | ||
| 9 | th(INCLKH-DV) | Hold time, CHn_DATA/XDATA valid after CHn_CLK high | 0.8 | ns | ||
| 10 | tsu(DV-INCLKL) | Setup time, CHn_DATA/XDATA valid before CHn_CLK low | 4 | ns | ||
| 11 | th(INCLKL-DV) | Hold time, CHn_DATA/XDATA valid after CHn_CLK low | 0.8 | ns | ||
| 19 | tsu(WTV-OUTCLKL) | Setup time, CHn_WAIT valid before CHn_CLK high | 4 | ns | ||
| 20 | th(INCLKL-WTV) | Hold time, CHn_WAIT valid after CHn_CLK high | 0.8 | ns | ||
| 21 | tc(2xTXCLK) | Cycle time, 2xTXCLK input clock(1) | 6.66 | ns | ||