SPRS814D March 2012 – October 2019 TMS320C6655 , TMS320C6657
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| Byte Offset | Name | Description |
|---|---|---|
| 12 | options | See Figure 6-47 |
| 14 | Address Width | The number of bytes in the SPI device address. Can be 2 or 3 (16 or 24 bit) |
| 16 | NPin | The operational mode, 4 or 5 pin |
| 18 | Chipsel | The chip select used. Can be 0-3. |
| 20 | Mode | SPI mode, 0-3 |
| 22 | C2T Delay | SPI chip select active to transmit start delay value (0-255) |
| 24 | CPU Freq MHz | The speed of the CPU, in MHz |
| 26 | Bus Freq, MHz | The MHz portion of the SPI bus frequency. Default = 5MHz |
| 28 | Bus Freq, kHz | The kHz portion of the SPI buf frequency. Default = 0 |
| 30 | Read Addr MSW | The first address to read from, MSW (valid for 24 bit address width only) |
| 32 | Read Addr LSW | The first address to read from, LSW |
| 34 | Next chipsel | Chipsel value used after boot config table processing is complete |
| 36 | Next read MSW | The next read address, MSW after config table processing is complete |
| 38 | Next read LSW | The next read address, LSW after config table processing is complete |
The bus frequency programmed into the SPI by the boot ROM is from the table: MHz.kHz. So for a 5.1 MHz bus frequency the MHz value is 5, the kHz value is 100.
| 15 | 2 | 1 | 0 |
| Reserved | Mode | ||||||||||||||
| Parameter | Value | Description |
|---|---|---|
| Mode | 0 | Load a boot parameter table from the SPI |
| 1 | Load boot records from the SPI (boot tables) | |
| 2 | Load boot config records from the SPI (boot config tables) | |
| 3 | Reserved |