SPRS814D March 2012 – October 2019 TMS320C6655 , TMS320C6657
PRODUCTION DATA.
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| NO. | PARAMETER | MIN | MAX | UNIT | ||
|---|---|---|---|---|---|---|
| 12 | tc(OUTCLK) | Cycle time, CHn_CLK | SDR mode | 13.33 | ns | |
| DDR mode | 26.66 | |||||
| 13 | tw(OUTCLKH) | Pulse width, CHn_CLK high | SDR mode | 5 | ns | |
| DDR mode | 10 | |||||
| 14 | tw(OUTCLKL) | Pulse width, CHn_CLK low | SDR mode | 5 | ns | |
| DDR mode | 10 | |||||
| 15 | td(OUTCLKH-STV) | Delay time, CHn_START valid after CHn_CLK high | 1 | 11 | ns | |
| 16 | td(OUTCLKH-ENV) | Delay time, CHn_ENABLE valid after CHn_CLK high | 1 | 11 | ns | |
| 17 | td(OUTCLKH-DV) | Delay time, CHn_DATA/XDATA valid after CHn_CLK high | 1 | 11 | ns | |
| 18 | td(OUTCLKL-DV) | Delay time, CHn_DATA/XDATA valid after CHn_CLK low | 1 | 11 | ns | |
Figure 5-30 uPP Single Data Rate (SDR) Receive Timing
Figure 5-31 uPP Double Data Rate (DDR) Receive Timing
Figure 5-32 uPP Single Data Rate (SDR) Transmit Timing
Figure 5-33 uPP Double Data Rate (DDR) Transmit Timing