SPRS814D March 2012 – October 2019 TMS320C6655 , TMS320C6657
PRODUCTION DATA.
請參考 PDF 數據表獲取器件具體的封裝圖。
| NO. | MIN | MAX | UNIT | ||
|---|---|---|---|---|---|
| Master Mode Timing Diagrams — Base Timings for 3-Pin Mode | |||||
| 7 | tsu(SDI-SPC) | Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 0 | 2 | ns | |
| 7 | tsu(SDI-SPC) | Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 1 | 2 | ns | |
| 7 | tsu(SDI-SPC) | Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 0 | 2 | ns | |
| 7 | tsu(SDI-SPC) | Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 1 | 2 | ns | |
| 8 | th(SPC-SDI) | Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 0 | 5 | ns | |
| 8 | th(SPC-SDI) | Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 1 | 5 | ns | |
| 8 | th(SPC-SDI) | Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 0 | 5 | ns | |
| 8 | th(SPC-SDI) | Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 1 | 5 | ns | |