6.5.1.1 Internal Clocks and Maximum Operating Frequencies
The Main PLL, used to drive the CorePacs, the switch fabric, and a majority of the peripheral clocks (all but the DDR3) requires a PLL controller to manage the various clock divisions, gating, and synchronization. The PLL controller of the Main PLL has several SYSCLK outputs that follow, as well as the clock description. Each SYSCLK has a corresponding divider that divides down the output clock of the PLL. Dividers are not programmable unless explicitly mentioned in the following description.
- SYSCLK1: Full-rate clock for the CorePacs.
- SYSCLK2: 1/x-rate clock for CorePac emulation. The default rate for this is 1/3. It is programmable from /1 to /32, where this clock does not violate the max of 350 MHz. The SYSCLK2 can be turned off by software.
- SYSCLK3: 1/2-rate clock used to clock the MSMC, HyperLink, and DDR EMIF.
- SYSCLK4: 1/3-rate clock for the switch fabrics and fast peripherals. The Debug_SS and ETBs use this as well.
- SYSCLK5: 1/y-rate clock for the system trace module only. The default rate for this is 1/5. It is configurable and the max configurable clock is 210 MHz and min configurable clock is 32 MHz. The SYSCLK5 can be turned off by software.
- SYSCLK6: 1/64-rate clock. 1/64 rate clock (emif_ptv) used to clock the PVT-compensated buffers for DDR3 EMIF.
- SYSCLK7: 1/6-rate clock for slow peripherals (GPIO, UART, Timer, I2C, SPI, EMIF16, McBSP, and so forth.) and sources the SYSCLKOUT output pin.
- SYSCLK8: 1/z-rate clock. This clock is used as slow_sysclk in the system. Default is 1/64. It is programmable from /24 to /80.
- SYSCLK9: 1/12-rate clock for SmartReflex.
- SYSCLK10: 1/3-rate clock for SRIO only.
- SYSCLK11: 1/6-rate clock for PSC only.
Only SYSCLK2, SYSCLK5, and SYSCLK8 are programmable on the C665x device.
NOTE
In case any of the other programmable SYSCLKs are set slower than 1/64 rate, then SYSCLK8 (SLOW_SYSCLK) must be programmed to either match, or be slower than, the slowest SYSCLK in the system.