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6.5 Main PLL and PLL Controller

This section provides a description of the Main PLL and the PLL controller. For details on the operation of the PLL controller module, see the Phase-Locked Loop (PLL) for KeyStone Devices User's Guide.

The Main PLL is controlled by the standard PLL controller. The PLL controller manages the clock ratios, alignment, and gating for the system clocks to the device. Figure 6-3 shows a block diagram of the main PLL and the PLL controller.

TMS320C6655 TMS320C6657 Main_PLL_and_PLL_controller_f1.gif

Figure 6-3 Main PLL and PLL Controller

NOTE

PLLM[5:0] bits of the multiplier are controlled by the PLLM register inside the PLL controller and PLLM[12:6] bits are controlled by the chip-level MAINPLLCTL0 register. The complete 13-bit value is latched when the GO operation is initiated in the PLL controller. Only PLLDIV2, PLLDIV5, and PLLDIV8 are programmable on the C665x device. See the Phase-Locked Loop (PLL) for KeyStone Devices User's Guide for more details on how to program the PLL controller.

The multiplication and division ratios within the PLL and the post-division for each of the chip-level clocks are determined by a combination of this PLL and the PLL controller. The PLL controller also controls reset propagation through the chip, clock alignment, and test points. The PLL controller monitors the PLL status and provides an output signal indicating when the PLL is locked.

Main PLL power is supplied externally through the Main PLL power-supply pin (AVDDA1). An external EMI filter circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone Devices for detailed recommendations. For the best performance, TI recommends placing all the PLL external components on one side of the board without jumpers, switches, or components other than those shown. For reduced PLL jitter, maximize the spacing between switching signal traces and the PLL external components (C1, C2, and the EMI Filter).

The minimum SYSCLK rise and fall times should also be observed. For the input clock timing requirements, see Section 5.7.4.

NOTE

The PLL controller as described in the Phase-Locked Loop (PLL) for KeyStone Devices User's Guide includes a superset of features, some of which are not supported on the C665x device. The following sections describe the registers that are supported; it should be assumed that any registers not included in these sections is not supported by the device. Furthermore, only the bits within the registers described here are supported. Avoid writing to any reserved memory location or changing the value of reserved bits.

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6.5 Main PLL and PLL Controller