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ZHCSCK8H May 2014 – April 2025 LP8860-Q1

PRODUCTION DATA

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

VFP|32
- MPQF098C

散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)

VFP|32
- PPTD258B

訂購(gòu)信息

6.3.1.2 LED PWM Frequency and Resolution

LED output PWM frequency is selected with <PWM_FREQ[3:0]> EEPROM register when using a 5MHz internal oscillator for generating PWM output. <LED_STRING_CONF[2:0]> bits define phase shift between LED outputs as described later. <PWM_RESOLUTION[1:0]> EEPROM bits select the PLL output frequency and hence the LED PWM resolution. PWM frequencies with <EN_SYNC> = 0 are listed in Table 6-1.

Note:

If the VSYNC signal is used for generating PWM output frequency, it affects all clock frequencies, as well as the LED PWM output frequency. The Section 6.6.2 section explains how all the dividers affect the output clocks.

LP8860-Q1 PWM
Clocking With Internal Oscillator

Figure 6-2 PWM Clocking With Internal Oscillator

LP8860-Q1 PWM
Clocking With PLL, Internal Oscillator as Reference

Figure 6-3 PWM Clocking With PLL, Internal Oscillator as Reference

Table 6-1 Output PWM Frequency and Resolution With Internal Oscillator

		00 OSC = 5MHz	01 OSC = 10MHz	10 OSC = 20MHz	11 OSC = 40MHz
PWM_FREQ[3:0]	PWM_RESOLUTION[1:0] PWM FREQUENCY (Hz)	RESOLUTION (bit)
1111	39063	7	8	9	10
1110	34180	7	8	9	10
1101	30518	7	8	9	10
1100	29297	7	8	9	10
1011	28076	7	8	9	10
1010	26855	7	8	9	10
1001	25635	7	8	9	10
1000	24412	7	8	9	10
0111	23192	7	8	9	10
0110	21973	7	8	9	10
0101	20752	7	8	9	10
0100	19531	8	9	10	11
0011	17090	8	9	10	11
0010	13428	8	9	10	11
0001	9766	9	10	11	12
0000	4883	10	11	12	13

LP8860-Q1 PWM
Synchronization With External VSYNC Input

Figure 6-4 PWM Synchronization With External VSYNC Input

PWM clock frequencies with different <SEL_DIVIDER>, <EN_PLL>, and <EN_SYNC> combinations are listed in Table 6-2.

Table 6-2 PLL Clock and LED PWM Frequency

PWM_SYNC	SEL_DIVIDER	EN_PLL	EN_SYNC	PLL CLOCK	PWM FREQUENCY
0	X	0	0	5MHz	See Table 6-1
0	1	1	0	5, 10, 20, 40MHz	See Table 6-1
0	0	1	1	SYNC × R_SEL[1:0] × SLOW_PLL_DIV[12:0]/ SYNC_PRE_DIV[3:0]	PLL clock / GEN_DIV
1	0	1	1	SYNC × GEN_DIV × SLOW_PLL_DIV[12:0]/ SYNC_PRE_DIV[3:0]	PLL clock / GEN_DIV

GEN_DIV coefficients and resolution (bit) are listed on Table 6-3.

Table 6-3 GEN_DIV Coefficients and Resolution

	PWM_RESOLUTION[1:0]
	00			01			10			11
PWM_ FREQ[3:0]	STEP	GEN_DIV	RES (bits)	STEP	GEN_DIV	RES (bits)	STEP	GEN_DIV	RES (bits)	STEP	GEN_DIV	RES (bits)
0000	64	1024.00	10	32	2048.00	11	16	4096.00	12	8	8192.00	13
0001	128	512.00	9	64	1024.00	10	32	2048.00	11	16	4096.00	12
0010	176	372.36	8	88	744.73	9	44	1489.45	10	22	2978.91	11
0011	224	292.57	8	112	585.14	9	56	1170.29	10	28	2340.57	11
0100	256	256.00	8	128	512.00	9	64	1024.00	10	32	2048.00	11
0101	272	240.94	7	136	481.88	8	68	963.76	9	34	1927.53	10
0110	288	227.56	7	144	455.11	8	72	910.22	9	36	1820.44	10
0111	304	215.58	7	152	431.16	8	76	862.32	9	38	1724.63	10
1000	320	204.80	7	160	409.60	8	80	819.20	9	40	1638.40	10
1001	336	195.05	7	168	390.10	8	84	780.19	9	42	1560.38	10
1010	352	186.18	7	176	372.36	8	88	744.73	9	44	1489.45	10
1011	368	178.09	7	184	356.17	8	92	712.35	9	46	1424.70	10
1100	384	170.67	7	192	341.33	8	96	682.67	9	48	1365.33	10
1101	400	163.84	7	200	327.68	8	100	655.36	9	50	1310.72	10
1110	448	146.29	7	224	292.57	8	112	585.14	9	56	1170.29	10
1111	512	128.00	7	256	256.00	8	128	512.00	9	64	1024.00	10

Dithering allows increased resolution and smaller average steps size. Dithering can be programmed with EEPROM bits <DITHER[2:0]> 0 to 4 bits. Figure 6-5 shows 1-bit dithering. For 3-bit dithering, every 8^th pulse is made 1 LSB longer to increase the average value by 1/8^th. Dither is available in steady state condition when <EN_STEADY_DITHER> is high, otherwise during slope only.

LP8860-Q1 Example
of the Dithering, 1-Bit Dither, 10-Bit Resolution

Figure 6-5 Example of the Dithering, 1-Bit Dither, 10-Bit Resolution