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SLUSFZ6 September 2025 UCC218915-Q1

ADVANCE INFORMATION

請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DFP|28

散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)

5.7 Electrical Characteristics

VCC = 3.3 V or 5.0 V, 1-μF capacitor from VCC to GND, VDD - COM and COM - VEE over recommended operating conditions unless otherwise noted, no external capacitor on VBN or VBP, C_L = 100 pF, -40℃ < T_J < 150℃ (unless otherwise noted)⁽¹⁾⁽²⁾.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER SUPPLY QUIESCENT CURRENT
I_VCCQ	VCC quiescent current	IN+ = GND, IN- = GND, f_s = 0 Hz	1	2	3	mA
I_VCCQ	VCC quiescent current	IN+ = VCC, IN- = GND, f_s = 0 Hz	3	4	5.5	mA
I_VDDQ	VDD quiescent current	IN+ = GND, IN- = GND, f_s = 0 Hz	3	5	7	mA
I_VDDQ	VDD quiescent current	IN+ = VCC, IN- = GND, f_s = 0 Hz	4	7	10	mA
I_VEEQ	VEE quiescent current	IN+ = GND, IN- = GND, f_s = 0 Hz, VEE = -5 V	-5	-3.5	-2	mA
I_VEEQ	VEE quiescent current	IN+ = VCC, IN- = GND, f_s = 0 Hz, VEE = -5 V	-5	-3.5	-2	mA
POWER SUPPLY PROTECTION
V_{VCC_ON}	VCC UVLO rising threshold		2.5	2.6	2.75	V
V_{VCC_OFF}	VCC UVLO falling threshold		2.4	2.5	2.65	V
V_{VCC_HYST}	VCC UVLO hysteresis			100		mV
t_VCCFIL	VCC UVLO deglitch time			5		μs
t_{VCC+ to OUT}	VCC UVLO on delay to OUTN low	IN+ = VCC, IN- = GND		tbd	15	μs
t_{VCC- to OUT}	VCC UVLO off delay to OUTP high	IN+ = VCC, IN- = GND			11	μs
t_{VCC+ to RDY}	VCC UVLO on delay to RDY high	RST/EN = VCC		tbd	20	μs
t_{VCC- to RDY}	VCC UVLO off delay to RDY low	RST/EN = VCC			11	μs
V_{VDD_UVLO_ON}	VDD UVLO rising threshold		11.4	12	12.6	V
V_{VDD_UVLO_OFF}	VDD UVLO falling threshold		10.45	11	11.55	V
V_{VDD_HYST}	VDD UVLO hysteresis			1		V
t_VDDFIL	VDD UVLO deglitch time			5		μs
t_{VDD+ to OUT}	VDD UVLO on delay to OUTN low	IN+ = VCC, IN- = GND			10	μs
t_{VDD- to OUT}	VDD UVLO off delay to OUTP high	IN+ = VCC, IN- = GND			10	μs
t_{VDD+ to RDY}	VDD UVLO on delay to RDY high	RST/EN = FLT = VCC			15	μs
t_{VDD- to RDY}	VDD UVLO off delay to RDY low	RST/EN = FLT = VCC			15	μs
LOW VOLTAGE SIDE LOGIC INPUTS (IN+, IN-, RST/EN)
V_INH	Input High Threshold			0.57xV_CC	0.7xV_CC	V
V_INL	Input low threshold		0.3xV_CC	0.42xV_CC		V
V_INHYS	Input threshold hysteresis			0.15xV_CC		V
I_IH	Input high level input leakage current	V_IN = VCC, VCC = 5 V		50		uA
I_IL	Input low level input leakage current	V_IN = GND, VCC = 5V		-50		uA
R_IND	Input pins pull down resistance			100		k?
R_INU	Input pins pull up resistance			100		k?
t_INFIL	IN+, IN– and RST/EN deglitch (ON and OFF) filter time	f_S = 50kHz		25		ns
t_RSTFIL	Deglitch filter time to reset FLT		400	650	800	ns
GATE DRIVER STAGE
I_OUTP	Peak source and sink current for OUTP		1.5	2.8		A
I_OUTN	Peak source and sink current for OUTN		1.5	2.8		A
V_{OUTP_L}	OUTP low-level output voltage		VDD-13	VDD-11	VDD-9	V
V_{OUTN_H}	OUTN high-level output voltage, referenced to VEE		9	11	13	V
t_OUTDT	Deadtime between OUTP and OUTN transitions		25	50	85	ns
EXTERNAL MILLER CLAMP
V_CLMPTH	Miller clamp threshold voltage	Reference to VEE	1.7	2.0	2.3	V
V_CLMPE	Output high voltage	Reference to VEE	9	11	13	V
I_CLMPEH	Peak source current	C_CLMPE = 10nF		0.5		A
I_CLMPEL	Peak sink current	C_CLMPE = 10nF		0.5		A
t_CLMPER	CLMPE rise time (10% to 90%)⁽³⁾	C_CLMPE = 330pF		5	20	ns
t_DCLMPE	Miller clamp ON delay time	C_CLMPE = 330pF		35	60	ns
DESAT PROTECTION
I_CHG	Blanking capacitor charge current	V_DESAT = 2.0V		2000		μA
I_DCHG	Blanking capacitor discharge current	V_DESAT = 6.0V		50		mA
V_DESATTH	Detection threshold		8.5	9	9.5	V
t_DESATLEB	Leading edge blank time			200		ns
t_DESATFIL	DESAT deglitch filter		80	125	170	ns
t_DESATOFF	DESAT propagation delay to OUTP high	V_DESAT>V_DESATTH	150	200	300	ns
t_DESATFLT	DESAT to FLT low delay				10	μs
SOFT SHUTDOWN (SSD)
I_SSD	Soft shutdown sink current	V_SSD-COM = 8 V	0.5	1	1.65	A
t_SSD	Soft shutdown activation time		1.5	2	2.5	μs
R_SSD	Soft shutdown pull-down resistance	I_SSD = 0.1A		1.9		?
OVERTEMPERATURE PROTECTION
T_TSDTH	Thermal shutdown rising threshold		155			℃
T_TSDHYST	Thermal shutdown hysteresis			20		℃
ACTIVE SHORT CIRCUIT (ASC)
V_ASCL	ASC input low threshold referenced to COM		1.2	1.45	1.7	V
V_ASCH	ASC input high threshold referenced to COM		2.3	2.7	3.1	V
R_ASCD	ASC input pulldown resistance			100		k?
t_ASCFIL	ASC deglitch filter time		400		700	ns
t_{ASC_r}	ASC on delay to OUTN low				1	μs
t_{ASC_f}	ASC off delay to OUTP high				1	μs
t_{ASC_FB}	ASC to ASC_FB delay				10	μs
FAULT REPORTING (FLT, RDY)
t_RDYHLD	VDD UVLO RDY low minimum holding time				100	μs
t_FLTMUTE	Output mute time on overcurrent fault	Reset fault through RST/EN			100	μs
R_ODON	Open drain output on resistance	I_ODON = 10mA			30	?
COMMON MODE TRANSIENT IMMUNITY
CMTI	CMTI noise immunity	V_CM = 1500 V	200			V/ns

(1) Currents are positive into and negative out of the specified terminal.

(2) All voltages are referenced to COM unless otherwise noted

(3) Timing thresholds for OUTP, OUTN, and CLMPE are 0.9V and 8.1V (10% and 90% of min value)