During the turn on and turn off switching transient, the peak source and sink current is provided by the VDD and VEE power supply through the buffer FETs. The large peak current is possible to drain the VDD and VEE voltage level and cause a voltage droop on the power supplies. To stabilize the power supply and ensure a reliable operation, a set of decoupling capacitors are recommended at the power supplies close to the gate driver VDD and VEE pins as well as close to the buffer FETs. A 10μF bypass cap is recommended between VDD and COM, VEE and COM as close to the buffer FETs as possible. A 1μF bypass cap is recommended between VDD and COM, VEE and COM, and VCC and GND close to the gate driver. A 0.1μF decoupling cap is also recommended for each power supply to filter out high frequency noise. The decoupling capacitors must be low ESR and ESL to avoid high frequency noise, and should be placed as close as possible to the VCC, VDD and VEE pins to prevent noise coupling from the system parasitics of PCB layout.