The output stage of the is designed to drive a complimentary pair of external buffer MOSFETs in a push-pull configuration. The PMOS driver (OUTP) and the NMOS driver (OUTN) can each source and sink 2.8A making it suitable for driving a wide range of buffer MOSFETs to cover a wide range of power levels. OUTP and OUTN are driven complimentary with a deadtime, t_OUTDT, to prevent cross conduction. OUTP drives the gate of an external PMOS between VDD and VBP, which is an internally generated rail that is 11V below VDD. OUTN drives the gate of an external NMOS between VEE and VBN, which is an internally generated rail that is 11V above VEE. A simplified schematic of the pre-driver architecture is shown in Figure 6-4.

Figure 6-4 Pre-Driver Output Architecture

Input-to-output states are given in Table 6-1 where ASC is not active and no system faults are present. A timing diagram showing the relationship betweein inputs and outputs is shown in Figure 6-5. Propagation delays from input-to-output, deadtime between OUTN and OUTP transitions, and rise and fall times of the output signals are shown.

Figure 6-5 Input-to-Output Timing Diagram