The UCC218915-Q1 has an active Miller clamp function to add an additional low impedance path to prevent unintentional turn-on while the driver is in the OFF state. In half-bridge applications it is possible for the body diode of the power semiconductor device to conduct while the driver is in the OFF state during deadtime. When this occurs, and the other power semiconductor device in the phase leg turns on, the drain-to-source or collector-to-emitter voltage will increase rapidly, causing high dV/dt across the Miller capacitance. This high dV/dt induces a current spike that can charge the gate capacitance and cause shoot-through if the main turn-off path isn't strong enough due to an external turn-off resistor, long PCB routing traces, or both.

The external active Miller clamp function provides a gate drive signal to drive an external Miller clamp FET. The FET is turned on when the power semiconductor device gate voltage is less than the Miller clamp threshold, V_CLMPTH. The gate voltage is sensed through the SSD/GATE pin. A simplified block diagram is shown in Figure 6-6 and a timing diagram is shown in Figure 6-7.

Figure 6-6 External Active Miller Clamp

Figure 6-7 External Active Miller Clamp Timing Diagram