The UCC218915-Q1 implements UVLO protection features for VCC and VDD. When the supply voltage is lower than the threshold voltage, the NMOS buffer FET driver output, OUTN, is held on so that the main power switch will be held off. The driver output will not turn on the PMOS buffer FET until all of the supplies are above the UVLO thresholds. The UVLO protection feature not only reduces the power consumption of the driver itself during low voltage power supply conditions, but also increases the efficiency of the power stage. For SiC MOSFETs and IGBTs, the on-resistance reduces while the gate-source voltage or gate-emitter voltage increases. If the power semiconductor is turned on with a low VDD value, the conduction loss increases significantly and can lead to a thermal issue and efficiency reduction of the power stage.

The UVLO protection blocks feature comparator thresholds with hysteresis and deglitch filters on the inputs to help improve noise immunity of the power supply. During the turn-on and turn-off switching transients, the driver sources and sinks a peak transient current from the power supply, which can result in sudden voltage drop of the power supply. With hysteresis and UVLO deglitch filters, the internal UVLO protection blocks will ignore small noises during the normal switching transients.

The RDY pin on the input side is used to indicate power good condition. The RDY pin is open drain. During UVLO conditions, the RDY pin is held low and connected to GND. Normally the pin is pulled up externally to VCC to indicate power is good.

Timing digrams of the UVLO protection feature of VCC and VDD are shown in Figure 6-1 and Figure 6-2.

Figure 6-1 VCC Protection Timing Diagram

Figure 6-2 VDD Protection Timing Diagram