SPRS814D March 2012 – October 2019 TMS320C6655 , TMS320C6657
PRODUCTION DATA.
請參考 PDF 數據表獲取器件具體的封裝圖。
This register is used to configure the type of reset initiated by RESET, watchdog timer and the RSTCTRL Register of the PLL controller; that is, a hard reset or a soft reset. By default, these resets will be hard resets. The Reset Configuration Register (RSTCFG) is shown in Figure 6-11 and described in Table 6-17.
| 31 | 14 | 13 | 12 | 11 | 4 | 3 | 0 | ||||||||
| Reserved | PLLCTLRST
TYPE |
RESETTYPE | Reserved | WDTYPE[N(1)] | |||||||||||
| R-0 | R/W-0(2) | R/W-02 | R-0 | R/W-02 | |||||||||||
| Legend: R = Read only; R/W = Read/Write; -n = value after reset |
| BIT | FIELD | DESCRIPTION |
|---|---|---|
| 31-14 | Reserved | Reserved. |
| 13 | PLLCTLRSTTYPE | PLL controller initiates a software-driven reset of type:
|
| 12 | RESETTYPE | RESET initiates a reset of type:
|
| 11-4 | Reserved | Reserved. |
| 3 | WDTYPE3 | Watchdog timer [N] initiates a reset of type:
|
| 2 | WDTYPE2 | Watchdog timer [N] initiates a reset of type:
|
| 1 | WDTYPE1 | Watchdog timer [N] initiates a reset of type:
|
| 0 | WDTYPE0 | Watchdog timer [N] initiates a reset of type:
|