ZHCSU60A May 2023 – January 2024 PCMD3180-Q1
PRODUCTION DATA
本節(jié)提供了一個(gè)典型的 EVM I2C 寄存器控制腳本，其中顯示了如何將 PCMD3180-Q1 設(shè)置為八通道數(shù)字 PDM 麥克風(fēng)錄音模式。
# Key: w 98 XX YY ==> write to I2C address 0x98, to register 0xXX, data 0xYY
# # ==> comment delimiter
#
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device. Note that there are
# other valid sequences depending on which features are used.
#
# See the PCMD3180-Q1 EVM user guide for jumper settings and audio connections.
#
# PDM 8-channel : PDMDIN1 - Ch1 and Ch2, PDMDIN2 - Ch3 and Ch4,
# PDMDIN3 - Ch5 and Ch6, PDMDIN4 - Ch7 and Ch8
# PDMCLKx = 2.8224 MHz (PDMCLKx/FSYNC = 64)
# FSYNC = 44.1 kHz (Output Data Sample Rate), BCLK = 11.2896 MHz (BCLK/FSYNC = 256)
################################################################
#
#
# Power up IOVDD and AVDD power supplies keeping SHDNZ pin voltage LOW
# Wait for IOVDD and AVDD power supplies to settle to steady state operating voltage range.
# Release SHDNZ to HIGH.
# Wait for 1ms.
#
# Wake-up device by I2C write into P0_R2 using internal AREG
w 98 02?81
#
# Configure CH1_INSRC as Digital PDM Input by I2C write into P0_R60
w 98 3C 40
#
# Configure CH2_INSRC as Digital PDM Input by I2C write into P0_R65
w 98 41 40
#
# Configure CH3_INSRC as Digital PDM Input by I2C write into P0_R70
w 98 46 40
#
# Configure CH4_INSRC as Digital PDM Input by I2C write into P0_R75
w 98 4B 40
#
# Configure PDMCLK1_GPO1 as PDMCLK by I2C write into P0_R34
w 98 22 41
#
# Configure PDMCLK1_GPO2 as PDMCLK by I2C write into P0_R35
w 98 23 41
#
# Configure PDMCLK1_GPO3 as PDMCLK by I2C write into P0_R36
w 98 24 41
#
# Configure PDMCLK1_GPO4 as PDMCLK by I2C write into P0_R37
w 98 25 41
#
# Configure PDMDIN1_GPI1 and PDMDIN2_GPI2 as PDMDIN1 and PDMDIN2 by I2C write into P0_R43
w 98 2B 45
#
# Configure PDMDIN3_GPI3 and PDMDIN4_GPI4 as PDMDIN3 and PDMDIN4 by I2C write into P0_R44
w 98 2C 67
#
# Enable Input Ch-1 to Ch-8 by I2C write into P0_R115
w 98 73 FF
#
# Enable ASI Output Ch-1 to Ch-8 slots by I2C write into P0_R116
w 98 74 FF
#
# Power-up PDM converter and PLL by I2C write into P0_R117
w 98 75 60
#
# Apply FSYNC = 44.1 kHz and BCLK = 11.2896 MHz and
# Start recording data by host on ASI bus with TDM protocol 32-bits channel wordlength