SLVSGJ9A May 2024 – October 2025 DRV7308
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Pin Configuration and Functions
- 5 Absolute Maximum Ratings
- 6 ESD Ratings
- 7 Recommended Operating Conditions
- 8 Thermal Information
- 9 Electrical Characteristics
- 10Timing Diagrams
- 11Typical Characteristics
-
12Detailed Description
- 12.1 Overview
- 12.2 Functional Block Diagram
- 12.3 Feature Description
- 12.4 Protections
- 13Application and Implementation
- 14Layout
- 15Revision History
- 16Device and Documentation Support
- 17Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
12.3.9.3 Logic-Level Input Pin (Internal Pulldown)
Figure 12-3 shows the input structure for the logic level pins EN, INHx, INLx, ILIMIT, BRAKE. The input can be with a voltage or external resistor.
Figure 12-5 Logic-Level Input Pin
Structure