SLVSGJ9A May 2024 – October 2025 DRV7308
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Pin Configuration and Functions
- 5 Absolute Maximum Ratings
- 6 ESD Ratings
- 7 Recommended Operating Conditions
- 8 Thermal Information
- 9 Electrical Characteristics
- 10Timing Diagrams
- 11Typical Characteristics
-
12Detailed Description
- 12.1 Overview
- 12.2 Functional Block Diagram
- 12.3 Feature Description
- 12.4 Protections
- 13Application and Implementation
- 14Layout
- 15Revision History
- 16Device and Documentation Support
- 17Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
4 Pin Configuration and Functions
Figure 4-1 DRV7308 VQFN With Exposed
Thermal Pad Top ViewTable 4-1 Pin Functions
| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| AMPIN- | 5 | I | Inverting input of the operational amplifier |
| AMPIN+ | 6 | I | Non-inverting input of the operational amplifier |
| AMPOUT | 4 | O | Output terminal of the operational amplifier |
| BOOTA | 48 | P | Bootstrap supply for phase A; A GVDD rated capacitor must be placed between BOOTA and OUTA. |
| BOOTB | 43 | P | Bootstrap supply for phase B; A GVDD rated capacitor must be placed between BOOTB and OUTB. |
| BOOTC | 41 | P | Bootstrap supply for phase C; A GVDD rated capacitor must be placed between BOOTC and OUTC. |
| BRAKE | 25 | I | Motor Brake signal. Logic high on the pin turns on all the low side GaN FETs and turns off all the high side GaN FETs |
| EN | 64 | I | Driver enable pin. When this pin is logic low the device goes to shutdown mode and all the GaN FETs are turned off. A 20μs to 40μs low pulse can be used to reset fault conditions |
| nFAULT | 26 | O | Fault indication pin. Pulled logic-low on fault condition; Open-drain output requires an external pullup |
| ILIMIT | 2 | I | Reference voltage for internal overcurrent limit comparator |
| INHA | 18 | I | High-side driver control input for OUTA. This pin controls the output of the high-side GaN FET |
| INHB | 20 | I | High-side driver control input for OUTB. This pin controls the output of the high-side GaN FET |
| INHC | 22 | I | High-side driver control input for OUTC. This pin controls the output of the high-side GaN FET |
| INLA | 19 | I | Low-side driver control input for OUTA. This pin controls the output of the low-side GaN FET |
| INLB | 21 | I | Low-side driver control input for OUTB. This pin controls the output of the low-side GaN FET |
| INLC | 24 | I | Low-side driver control input for OUTC. This pin controls the output of the low-side GaN FET |
| NC | 1, 23 | No connect, can be connected to GND | |
| RSVD_A | 49 | I | Reserved pin. Connect the pin to OUTA |
| RSVD_B | 44 | I | Reserved pin. Connect the pin to OUTB |
| RSVD_C | 40 | I | Reserved pin. Connect the pin to OUTC |
| OUTA | 50-57 | P | Half bridge output A |
| OUTB | 42, 45-47, 72 | P | Half bridge output B |
| OUTC | 32-39 | P | Half bridge output C |
| GND | 7, 17, 27,28,29, 60,61,62,66, 70, 71 | G | Device power and signal ground. Connect to system ground |
| SLA | 8, 9, 10, 67 | P | Phase A half bridge low side source |
| SLB | 11, 12, 13, 68 | P | Phase B half bridge low side source |
| SLC | 14, 15, 16, 69 | P | Phase C half bridge low side source |
| SR | 65 | I | OUTx voltage slew rate control. Connect a resistor between SR pin and GND or SR pin to GVDD to configure the slew rate |
| GVDD | 63 | P | Low voltage power supply. bypass to GND with one 1μF, GVDD rated ceramic capacitor plus one bulk capacitor rated for GVDD |
| VM | 30, 31, 58, 59 | P | Power supply. Connect to motor supply voltage; bypass to GND with a 0.1μF capacitor plus one bulk capacitor rated for VM. The pins 30 and 31 are internally connected to the pins 58 and 59. |
| VTEMP | 3 | O | Temperature Sensor Output |
(1) I = Input, O = Output, I/O =
Input or Output, G = Ground, P = Power.