SLVSGJ9A May 2024 – October 2025 DRV7308
PRODUCTION DATA
If the die temperature near GaN FET exceeds the trip point of the thermal shutdown limit (TOTSD), all the GaNFETs are disabled, and the nFAULT pin is driven low. If OTSD event is detected due to high-side GaN FET temperature rise, the normal operation starts again (driver operation and the nFAULT pin is released) when the overtemperature condition clears and the fault is cleared through a 20μs to 40μs toggling pulse on the EN pin or by GVDD power recycling. If OTSD event is detected due to low-side GaN FET temperature rise, the normal operation starts again when the over temperature condition clears.