ZHCSHD7A January 2018 – April 2020 ADC12DJ2700
PRODUCTION DATA.
Table 44 lists the parameters that can be trimmed and the associated registers. User trimming is limited to foreground (FG) calibration only.
| TRIM PARAMETER | TRIM REGISTER | NOTES |
|---|---|---|
| Band-gap reference | BG_TRIM | Measurement on BG output pin. |
| Input termination resistance | RTRIM_x,
where x = A for INA± or B for INB±) |
The device must be powered on with a clock applied. |
| Input offset voltage | OADJ_x_VINy,
where x = ADC core (A or B) and y = A for INA± or B for INB±) |
Input offset adjustment in dual channel mode consists of changing OADJ_A_VINA for channel A and OADJ_B_VINB for channel B. In single channel mode, OADJ_A_VINx and OADJ_B_VINx must be adjusted together to trim the input offset or adjusted separate to compensate the fS/2 offset spur. |
| INA± and INB± gain | GAIN_TRIM_x,
where x = A for INA± or B for INB±) |
Set FS_RANGE_A and FS_RANGE_B to default values before trimming the input. Use FS_RANGE_A and FS_RANGE_B to adjust the full-scale input voltage. To trim the gain of ADC core A, change GAIN_B0 and GAIN_B1 together in the same direction. To trim the gain of ADC core B, change GAIN_B4 and GAIN_B5 together in the same direction. To trim the gain of the two banks within ADC A, change GAIN_B0 and GAIN_B1 in opposite directions. To trim the gain of the two banks within ADC B, change GAIN_B4 and GAIN_B5 in opposite directions. |
| INA± and INB± full-scale input voltage | FS_RANGE_x,
where x = A for INA± or B for INB±) |
Full-scale input voltage adjustment for each input. The default value is effected by GAIN_TRIM_x (x = A or B). Trim GAIN_TRIM_x with FS_RANGE_x set to the default value. FS_RANGE_x can then be used to trim the full-scale input voltage. |
| Intra-ADC core timing (bank timing) | Bx_TIME_y,
where x = bank number (0, 1, 4 or 5) and y = 0° or –90° clock phase |
Trims the timing between the two banks of an ADC core (ADC A or B). The 0° clock phase is used for dual channel mode and for ADC B in single channel mode. The –90° clock phase is used only for ADC A in single-channel mode. A mismatch in the timing between the two banks of an ADC core can result in an fS/2-fIN spur in dual channel mode or fS/4±fIN spurs in single channel mode. |
| Inter-ADC core timing (dual-channel mode) | TADJ_A, TADJ_B | The suffix letter (A or B) indicates the ADC core that is being trimmed. Changing either TADJ_A or TADJ_B adjusts the sampling instance of ADC A relative to ADC B in dual channel mode. |
| Inter-ADC core timing (single-channel mode) | TADJ_A_FG90, TADJ_B_FG0 | These trim registers are used to adjust the timing of ADC core A relative to ADC core B in single channel mode. A mismatch in the timing results in an fS/2-fIN spur that is signal dependent. Changing either TADJ_A_FG90 or TADJ_B_FG0 changes the relative timing of ADC core A relative to ADC core B in single channel mode. These registers are trimmed at production to optimize performance for INA±. |