ZHCSHD7A January 2018 – April 2020 ADC12DJ2700
PRODUCTION DATA.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SRC_EN | ||||||
| R/W-0000 000 | R/W-0 | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-1 | RESERVED | R/W | 0000 000 | RESERVED |
| 0 | SRC_EN | R/W | 0 | 0: SYSREF calibration disabled; use the TAD register to manually control the TAD[16:0] output and adjust the DEVCLK delay (default)
1: SYSREF calibration enabled; the DEVCLK delay is automatically calibrated; the TAD register is ignored A 0-to-1 transition on SRC_EN starts the SYSREF calibration sequence. Program SRC_CFG before setting SRC_EN. Ensure that ADC calibration is not currently running before setting SRC_EN. |