ZHCSHD7A January 2018 – April 2020 ADC12DJ2700
PRODUCTION DATA.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SER_PE | ||||||
| R/W-0000 | R/W-0000 | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | RESERVED | R/W | 0000 | RESERVED |
| 3-0 | SER_PE | R/W | 0000 | This field sets the pre-emphasis for the serial lanes to compensate for the low-pass response of the PCB trace. This setting is a global setting that affects all 16 lanes. |