ZHCSHD7A January 2018 – April 2020 ADC12DJ2700
PRODUCTION DATA.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PLL_ALM | LINK_ALM | REALIGNED_ALM | NCO_ALM | CLK_ALM | ||
| R/W-000 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | RESERVED | R/W | 000 | RESERVED |
| 4 | PLL_ALM | R/W | 1 | PLL lock lost alarm. This bit is set whenever the PLL is not locked. Write a 1 to clear this bit. |
| 3 | LINK_ALM | R/W | 1 | Link alarm. This bit is set whenever the JESD204B link is enabled, but is not in the DATA_ENC state. Write a 1 to clear this bit. |
| 2 | REALIGNED_ALM | R/W | 1 | Realigned alarm. This bit is set whenever SYSREF causes the internal clocks (including the LMFC) to be realigned. Write a 1 to clear this bit. |
| 1 | NCO_ALM | R/W | 1 | NCO alarm. This bit can be used to detect an upset to the NCO phase. This bit is set when any of the following occur:
Write a 1 to clear this bit. |
| 0 | CLK_ALM | R/W | 1 | Clock alarm. This bit can be used to detect an upset to the digital block and JESD204B clocks. This bit is set whenever the internal clock dividers for the A and B channels do not match. Write a 1 to clear this bit. |