ZHCSHD7A January 2018 – April 2020 ADC12DJ2700
PRODUCTION DATA.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DEVCLK_LVPECL_EN | SYSREF_LVPECL_EN | SYSREF_INVERTED | ||||
| R/W-0010 0 | R/W-0 | R/W-0 | R/W-0 | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-3 | RESERVED | R/W | 0010 0 | RESERVED |
| 2 | DEVCLK_LVPECL_EN | R/W | 0 | Activate low-voltage PECL mode for DEVCLK. |
| 1 | SYSREF_LVPECL_EN | R/W | 0 | Activate low-voltage PECL mode for SYSREF. |
| 0 | SYSREF_INVERTED | R/W | 0 | Inverts the SYSREF signal used for alignment. |