ZHCSHD7A January 2018 – April 2020 ADC12DJ2700
PRODUCTION DATA.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SOFT_RESET | RESERVED | ADDR_ASC | SDO_ACTIVE | RESERVED | |||
| R/W-0 | R-0 | R/W-1 | R-1 | R-0000 | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | SOFT_RESET | R/W | 0 | Setting this bit results in a full reset of the device. This bit is self-clearing. After writing this bit, the device may take up to 750 ns to reset. During this time, do not perform any SPI transactions. |
| 6 | RESERVED | R | 0 | RESERVED |
| 5 | ADDR_ASC | R/W | 1 | 0: Descend – decrement address while streaming reads/writes
1: Ascend – increment address while streaming reads/writes (default) |
| 4 | SDO_ACTIVE | R | 1 | Always returns 1, indicating that the device always uses 4-wire SPI mode. |
| 3-0 | RESERVED | R | 0000 | RESERVED |