ZHCSHD7A January 2018 – April 2020 ADC12DJ2700
PRODUCTION DATA.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LINK_UP | SYNC_STATUS | REALIGNED | ALIGNED | PLL_LOCKED | RESERVED | |
| R | R | R | R/W | R/W | R | R | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R | Undefined | RESERVED |
| 6 | LINK_UP | R | Undefined | When set, this bit indicates that the JESD204B link is up. |
| 5 | SYNC_STATUS | R | Undefined | Returns the state of the JESD204B SYNC~ signal.
0: SYNC~ asserted 1: SYNC~ de-asserted |
| 4 | REALIGNED | R/W | Undefined | When high, this bit indicates that an internal digital clock, frame clock, or multiframe (LMFC) clock phase was realigned by SYSREF. Write a 1 to clear this bit. |
| 3 | ALIGNED | R/W | Undefined | When high, this bit indicates that the multiframe (LMFC) clock phase has been established by SYSREF. The first SYSREF event after enabling the JESD204B encoder will set this bit. Write a 1 to clear this bit. |
| 2 | PLL_LOCKED | R | Undefined | When high, this bit indicates that the PLL is locked. |
| 1-0 | RESERVED | R | Undefined | RESERVED |