ZHCSHD7A January 2018 – April 2020 ADC12DJ2700
PRODUCTION DATA.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHASEAx[15:8] or PHASEBx[15:8] | |||||||
| R/W-0x00 | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHASEAx[7:0] or PHASEBx[7:0] | |||||||
| R/W-0x00 | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | PHASEAx or PHASEBx | R/W | See Table 126 | This value is MSB-justified into a 32-bit field and then added to the phase accumulator. This register can be interpreted as signed or unsigned; see the NCO Phase Offset Setting section. |