SPRZ450B February 2018 – September 2024 DRA74P , DRA75P , DRA76P , DRA77P
QSPI_SPI_CMD_REG [25:24] Masked from Read in RTL
Low
There is an integration error in the device. All WLEN (QSPI_SPI_CMD_REG[25:19]) bits in the QSPI_SPI_CMD_REG register are writeable. However, on a read the QSPI_SPI_CMD_REG[25:24] bits will be masked.
None.
SR 1.0
AM574x: 1.0
DRA75xP, DRA74xP, DRA77xP, DRA76xP: 1.0
TDA2Px: 1.0
AM576x: 1.0