Refresh Rate Issue after Warm Reset
DESCRIPTION
The refresh rate is programmed in the EMIF_SDRAM_REFRESH_CONTROL[15:0] REFRESH_RATE parameter and is calculated based off of the frequency of the DDR clock during normal operation.
When a warm reset is applied to the system, the DDR clock source is set to PLL bypass frequency which is much lower than the functional frequency of operation. Due to this frequency change, upon warm reset de-assertion the refresh rate will be too low until the DDR PLL is set to the functional frequency. This could result in unexpected behavior on the memory side.
WORKAROUND
There are 3 possible work-around options:
- Use workaround as outlined in Errata i862 to convert warm reset to PORz. Warm reset will function the same as cold reset with this approach.
- Use external circuitry to apply reset on DDR RESET# pin when warm reset is asserted. DDR contents will be erased upon warm reset with this approach.
- When warm reset is asserted, EMIF enters idle state and switches the external SDRAM device to self-refresh mode. The external SDRAM device switches to active mode after the warm reset time RSTTIME1. For more details on this behavior, see section Global Warm Reset Sequence of chapter Power, Reset, and Clock Management of the Device TRM.
To work around the issue in this advisory, program the CTRL_CORE_SMA_SW_0[6] WARM_SFORCE_EN bit to 1, which extends the self-refresh of the external SDRAM device until the CTRL_CORE_SMA_SW_0[5] WARM_SFORCE bit is cleared by software. Due to the self-refresh extension of the external SDRAM device, the DDR PLL is set back to functional frequency before EMIF enters active mode. For more details on CTRL_CORE_SMA_SW_0 register fields, see the CTRL_CORE_SMA_SW_0 register description in the Device TRM.
Note: Workaround #3 is the required workaround to preserve DDR contents during warm reset.
REVISIONS IMPACTED
SR 1.0
This erratum is considered negated on DRA75xP, DRA74xP, DRA77xP, DRA76xP SR 1.0 by implementing workaround #3.
AM574x: 1.0
DRA75xP, DRA74xP, DRA77xP, DRA76xP: 1.0
TDA2Px: 1.0
AM576x: 1.0