SPRZ450B February 2018 – September 2024 DRA74P , DRA75P , DRA76P , DRA77P
DPLL_VIDEOn May Require Multiple Lock Attempts
Medium
In rare circumstances the DPLL_VIDEO1 and DPLL_VIDEO2 PLLs may not lock on the first attempt during SoC initialization. When this occurs a subsequent attempt to relock the PLL will result in the PLL successfully locking.
In order to successfully lock the PLL, the following software sequence is recommended:
SR 1.0
AM574x: 1.0
DRA75xP, DRA74xP, DRA77xP, DRA76xP: 1.0
TDA2Px: 1.0
AM576x: 1.0