SPRZ450B February 2018 – September 2024 DRA74P , DRA75P , DRA76P , DRA77P
FPDLink PLL Unlocks With Certain SoC PLL M/N Values
Medium
FPD-Link SerDes are used to convert the Device’s parallel video output interfaces into high-speed serialized interfaces. To ensure proper operation, it is important for the Devices's video output clock to meet the input jitter requirements of the SerDes component clock input. At high frequencies, some Device PLL configurations, may produce a clock signal that does not comply with the FPD-Link specifications. These PLL configurations can potentially cause the FPD-Link deserializer to loose lock, producing flicker or blanking on the system display.
See application note SPRACA9 for information on how to best work around this issue in a given system.
SR 1.0
AM574x: 1.0
DRA75xP, DRA74xP, DRA77xP, DRA76xP: 1.0
TDA2Px: 1.0
AM576x: 1.0