SPRZ450B February 2018 – September 2024 DRA74P , DRA75P , DRA76P , DRA77P
PCIe Unaligned Read Access Issue
Medium
Access to the PCIe slave port that are not 32-bit aligned will result in incorrect mapping to TLP Address and Byte enable fields. Therefore, byte and half-word accesses are not possible to byte offset 0x1, 0x2, or 0x3.
To workaround this issue, there are two options:
SR 1.0
AM574x: 1.0
DRA75xP, DRA74xP, DRA77xP, DRA76xP: 1.0
TDA2Px: 1.0
AM576x: 1.0