DDR Access Hang after Warm Reset
DESCRIPTION
When warm reset is asserted, EMIF will preserve the contents of the DDR by entering self-refresh. During warm reset the DDR clock source is set to a slower PLL bypass than during normal operation. This causes the following JEDEC spec violations and could result in a DDR access hang after warm reset:
- DDR clock frequency to the DDR memory is lower than the JEDEC min. clock frequency specified as tCK(avg) min parameter in the JEDEC JESD79-3F DDR3 standard.
- Upon warm reset de-assertion, DDR is taken out of self-refresh and DDR clock frequency is changed from PLL bypass to normal operating frequency. This violates the JEDEC JESD79-3F DDR3 standard that requires input clock to be stable during normal operation.
WORKAROUND
There are 3 possible work-around options:
- Use workaround as outlined in Errata i862 to convert warm reset to PORz. Warm reset will function the same as cold reset with this approach.
- Use external circuitry to apply reset on DDR RESET# pin when warm reset is asserted. DDR contents will be erased upon warm reset with this approach.
- When warm reset is asserted, EMIF enters idle state and switches the external SDRAM device to self-refresh mode. The external SDRAM device switches to active mode after the warm reset time RSTTIME1. For more details on this behavior, see section Global Warm Reset Sequence of chapter Power, Reset, and Clock Management of the Device TRM.
To work around the issue in this advisory, program the CTRL_CORE_SMA_SW_0[6] WARM_SFORCE_EN bit to 1, which extends the self-refresh of the external SDRAM device until the CTRL_CORE_SMA_SW_0[5] WARM_SFORCE bit is cleared by software. Due to the self-refresh extension of the external SDRAM device, the DDR PLL is set back to functional frequency before EMIF enters active mode. For more details on CTRL_CORE_SMA_SW_0 register fields, see the CTRL_CORE_SMA_SW_0 register description in the Device TRM.
Note: Workaround #3 is the required workaround to preserve DDR contents during warm reset.
REVISIONS IMPACTED
SR 1.0
This erratum is considered negated on DRA75xP, DRA74xP, DRA77xP, DRA76xP SR 1.0 by implementing workaround #3.
AM574x: 1.0
DRA75xP, DRA74xP, DRA77xP, DRA76xP: 1.0
TDA2Px: 1.0
AM576x: 1.0