SPRZ450B February 2018 – September 2024 DRA74P , DRA75P , DRA76P , DRA77P
CSI Interface Setup/Hold Timing Does Not Meet MIPI DPHY Spec above 600MHz
Medium
When running the CSI2 interface at greater than 600MHz (1.2Gbps per lane), setup/hold times are not compliant with limits required by the MIPI CSI2 DPHY specification. Systems using the CSI2 interface at less than or equal to 600MHz are not affected.
Since the CSI2 interface includes up to 4 data lanes (plus 1 clock lane), data can be distributed across multiple lanes in order to keep the clock rate lower. Otherwise, the output delay timings of the external CSI2 transmitter device should be analyzed in comparison with the setup/hold timing requirements of the CSI2 receiver to confirm timing compatibility before attempting to run the interface at frequencies above 600MHz. Consult your local TI representative for more information on CSI2 receiver setup/hold timings at frequencies above 600MHz.
SR 1.0
DRA75xP, DRA74xP, DRA77xP, DRA76xP: 1.0
TDA2Px: 1.0
AM576x: 1.0