SPNS253A May 2018 – September 2019 TMS570LC4357-EP
PRODUCTION DATA.
| NO. | Parameter | MIN | MAX | Unit | ||
|---|---|---|---|---|---|---|
| 1 | tc(SPC)M | Cycle time, SPICLK(4) | 40 | 256tc(VCLK) | ns | |
| 2(5) | tw(SPCH)M | Pulse duration, SPICLK high (clock polarity = 0) | 0.5tc(SPC)M – tr(SPC)M – 3 | 0.5tc(SPC)M + 3 | ns | |
| tw(SPCL)M | Pulse duration, SPICLK low (clock polarity = 1) | 0.5tc(SPC)M – tf(SPC)M – 3 | 0.5tc(SPC)M + 3 | |||
| 3(5) | tw(SPCL)M | Pulse duration, SPICLK low (clock polarity = 0) | 0.5tc(SPC)M – tf(SPC)M – 3 | 0.5tc(SPC)M + 3 | ns | |
| tw(SPCH)M | Pulse duration, SPICLK high (clock polarity = 1) | 0.5tc(SPC)M – tr(SPC)M – 3 | 0.5tc(SPC)M + 3 | |||
| 4(5) | td(SPCH-SIMO)M | Delay time, SPISIMO valid before SPICLK low (clock polarity = 0) | 0.5tc(SPC)M – 6 | ns | ||
| td(SPCL-SIMO)M | Delay time, SPISIMO valid before SPICLK high (clock polarity = 1) | 0.5tc(SPC)M – 6 | ||||
| 5(5) | tv(SPCL-SIMO)M | Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) | 0.5tc(SPC)M – tf(SPC) – 4 | ns | ||
| tv(SPCH-SIMO)M | Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) | 0.5tc(SPC)M – tr(SPC) – 4 | ||||
| 6(5) | tsu(SOMI-SPCL)M | Setup time, SPISOMI before SPICLK low (clock polarity = 0) | tf(SPC) + 2.2 | ns | ||
| tsu(SOMI-SPCH)M | Setup time, SPISOMI before SPICLK high (clock polarity = 1) | tr(SPC) + 2.2 | ||||
| 7(5) | th(SPCL-SOMI)M | Hold time, SPISOMI data valid after SPICLK low (clock polarity = 0) | 10 | ns | ||
| th(SPCH-SOMI)M | Hold time, SPISOMI data valid after SPICLK high (clock polarity = 1) | 10 | ||||
| 8(6) | tC2TDELAY | Setup time CS active until SPICLK high (clock polarity = 0) | CSHOLD = 0 | C2TDELAY*tc(VCLK) + 2*tc(VCLK) - tf(SPICS) + tr(SPC) – 7 | (C2TDELAY+2) * tc(VCLK) - tf(SPICS) + tr(SPC) + 5.5 | ns |
| CSHOLD = 1 | C2TDELAY*tc(VCLK) + 3*tc(VCLK) - tf(SPICS) + tr(SPC) – 7 | (C2TDELAY+3) * tc(VCLK) - tf(SPICS) + tr(SPC) + 5.5 | ||||
| Setup time CS active until SPICLK low (clock polarity = 1) | CSHOLD = 0 | C2TDELAY*tc(VCLK) + 2*tc(VCLK) - tf(SPICS) + tf(SPC) – 7 | (C2TDELAY+2) * tc(VCLK) - tf(SPICS) + tf(SPC) + 5.5 | ns | ||
| CSHOLD = 1 | C2TDELAY*tc(VCLK) + 3*tc(VCLK) - tf(SPICS) + tf(SPC) – 7 | (C2TDELAY+3) * tc(VCLK) - tf(SPICS) + tf(SPC) + 5.5 | ||||
| 9(6) | tT2CDELAY | Hold time SPICLK low until CS inactive (clock polarity = 0) | 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) - tf(SPC) + tr(SPICS) - 7 | 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) - tf(SPC) + tr(SPICS) + 11 | ns | |
| Hold time SPICLK high until CS inactive (clock polarity = 1) | 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPC) + tr(SPICS) - 7 | 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPC) + tr(SPICS) + 11 | ns | |||
| 10 | tSPIENA | SPIENAn Sample point | (C2TDELAY+1) * tc(VCLK) - tf(SPICS) – 29 | (C2TDELAY+1)*tc(VCLK) | ns | |
| 11 | tSPIENAW | SPIENAn Sample point from write to buffer | (C2TDELAY+2)*tc(VCLK) | ns | ||
Figure 6-19 SPI Master Mode External Timing (CLOCK PHASE = 0)
Figure 6-20 SPI Master Mode Chip Select Timing (CLOCK PHASE = 0) | NO. | Parameter | MIN | MAX | Unit | ||
|---|---|---|---|---|---|---|
| 1 | tc(SPC)M | Cycle time, SPICLK (4) | 40 | 256tc(VCLK) | ns | |
| 2(5) | tw(SPCH)M | Pulse duration, SPICLK high (clock polarity = 0) | 0.5tc(SPC)M – tr(SPC)M – 3 | 0.5tc(SPC)M + 3 | ns | |
| tw(SPCL)M | Pulse duration, SPICLK low (clock polarity = 1) | 0.5tc(SPC)M – tf(SPC)M – 3 | 0.5tc(SPC)M + 3 | |||
| 3(5) | tw(SPCL)M | Pulse duration, SPICLK low (clock polarity = 0) | 0.5tc(SPC)M – tf(SPC)M – 3 | 0.5tc(SPC)M + 3 | ns | |
| tw(SPCH)M | Pulse duration, SPICLK high (clock polarity = 1) | 0.5tc(SPC)M – tr(SPC)M – 3 | 0.5tc(SPC)M + 3 | |||
| 4(5) | tv(SIMO-SPCH)M | Valid time, SPICLK high after SPISIMO data valid (clock polarity = 0) | 0.5tc(SPC)M – 6 | ns | ||
| tv(SIMO-SPCL)M | Valid time, SPICLK low after SPISIMO data valid (clock polarity = 1) | 0.5tc(SPC)M – 6 | ||||
| 5(5) | tv(SPCH-SIMO)M | Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0) | 0.5tc(SPC)M – tr(SPC) – 4 | ns | ||
| tv(SPCL-SIMO)M | Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1) | 0.5tc(SPC)M – tf(SPC) – 4 | ||||
| 6(5) | tsu(SOMI-SPCH)M | Setup time, SPISOMI before SPICLK high (clock polarity = 0) | tr(SPC) + 2.2 | ns | ||
| tsu(SOMI-SPCL)M | Setup time, SPISOMI before SPICLK low (clock polarity = 1) | tf(SPC) + 2.2 | ||||
| 7(5) | tv(SPCH-SOMI)M | Valid time, SPISOMI data valid after SPICLK high (clock polarity = 0) | 10 | ns | ||
| tv(SPCL-SOMI)M | Valid time, SPISOMI data valid after SPICLK low (clock polarity = 1) | 10 | ||||
| 8(6) | tC2TDELAY | Setup time CS active until SPICLK high (clock polarity = 0) | CSHOLD = 0 | 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) - tf(SPICS) + tr(SPC) – 7 | 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) - tf(SPICS) + tr(SPC) + 5.5 | ns |
| CSHOLD = 1 | 0.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) - tf(SPICS) + tr(SPC) – 7 | 0.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) - tf(SPICS) + tr(SPC) + 5.5 | ||||
| Setup time CS active until SPICLK low (clock polarity = 1) | CSHOLD = 0 | 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) - tf(SPICS) + tf(SPC) – 7 | 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) - tf(SPICS) + tf(SPC) + 5.5 | ns | ||
| CSHOLD = 1 | 0.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) - tf(SPICS) + tf(SPC) – 7 | 0.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) - tf(SPICS) + tf(SPC) + 5.5 | ||||
| 9(6) | tT2CDELAY | Hold time SPICLK low until CS inactive (clock polarity = 0) | T2CDELAY*tc(VCLK) + tc(VCLK) - tf(SPC) + tr(SPICS) - 7 | T2CDELAY*tc(VCLK) + tc(VCLK) - tf(SPC) + tr(SPICS) + 11 | ns | |
| Hold time SPICLK high until CS inactive (clock polarity = 1) | T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPC) + tr(SPICS) - 7 | T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPC) + tr(SPICS) + 11 | ns | |||
| 10 | tSPIENA | SPIENAn Sample Point | (C2TDELAY+1)* tc(VCLK) - tf(SPICS) – 29 | (C2TDELAY+1)*tc(VCLK) | ns | |
| 11 | tSPIENAW | SPIENAn Sample point from write to buffer | (C2TDELAY+2)*tc(VCLK) | ns | ||
Figure 6-21 SPI Master Mode External Timing (CLOCK PHASE = 1)
Figure 6-22 SPI Master Mode Chip Select Timing (CLOCK PHASE = 1)