| GCLK1 |
SYS.CDDIS.0 |
OSCIN |
SYS.GHVSRC[3:0] |
- This the main clock from which HCLK is divided down
- In phase with HCLK
- Is disabled separately from HCLK through the CDDISx registers bit 0
- Can be divided-by-1 up to 8 when running CPU self-test (LBIST) using the CLKDIV field of the STCCLKDIV register at address 0xFFFFE108
|
| GCLK2 |
SYS.CDDIS.0 |
OSCIN |
SYS.GHVSRC[3:0] |
- Always the same frequency as GCLK1
- 2 cycles delayed from GCLK1
- Is disabled along with GCLK1
- Gets divided by the same divider setting as that for GCLK1 when running CPU self-test (LBIST)
|
| HCLK |
SYS.CDDIS.1 |
OSCIN |
SYS.GHVSRC[3:0] |
- Divided from GCLK1 through HCLKCNTLregister
- Allowable clock ratio from 1:1 to 4:1
- Is disabled through the CDDISx registers bit 1
|
| VCLK |
SYS.CDDIS.2 |
OSCIN |
SYS.GHVSRC[3:0] |
- Divided down from HCLK through CLKCNTL register
- Can be HCLK/1, HCLK/2,... or HCLK/16
- Is disabled separately from HCLK through the CDDISx registers bit 2
- HCLK:VCLK2:VCLK must be integer ratios of each other
|
| VCLK2 |
SYS.CDDIS.3 |
OSCIN |
SYS.GHVSRC[3:0] |
- Divided down from HCLK
- Can be HCLK/1, HCLK/2,... or HCLK/16
- Frequency must be an integer multiple of VCLK frequency
- Is disabled separately from HCLK through the CDDISx registers bit 3
|
| VCLK3 |
SYS.CDDIS.8 |
OSCIN |
SYS.GHVSRC[3:0] |
- Divided down from HCLK
- Can be HCLK/1, HCLK/2,... or HCLK/16
- Is disabled separately from HCLK through the CDDISx registers bit 8
|
| VCLKA1 |
SYS.CDDIS.4 |
VCLK |
SYS.VCLKASRC[3:0] |
- Defaults to VCLK as the source
- Is disabled through the CDDISx registers bit 4
|
| VCLKA2 |
SYS.CDDIS.5 |
VCLK |
SYS.VCLKASRC[3:0] |
- Defaults to VCLK as the source
- Is disabled through the CDDISx registers bit 5
|
| VCLKA4 |
SYS.CDDIS.11 |
VCLK |
SYS.VCLKACON1[19:16] |
- Defaults to VCLK as the source
- Is disabled through the CDDISx registers bit 11
|
| VCLKA4_DIVR |
SYS.VCLKACON1.20 |
VCLK |
SYS.VCLKACON1[19:16] |
- Divided down from VCLKA4 using the VCLKA4R field of the VCLKACON1 register
- Frequency can be VCLKA4/1, VCLKA4/2, ..., or VCLKA4/8
- Default frequency is VCLKA4/2
- Is disabled separately through the VCLKA4_DIV_CDDIS bit in the VCLKACON1 register, if the VCLKA4 is not already disabled
|
| RTICLK1 |
SYS.CDDIS.6 |
VCLK |
SYS.RCLKSRC[3:0] |
- Defaults to VCLK as the source
- If a clock source other than VCLK is selected for RTICLK1, then the RTICLK1 frequency must be less than or equal to VCLK/3
- Application can ensure this by programming the RTI1DIV field of the RCLKSRC register, if necessary
- Is disabled through the CDDISx registers bit 6
|