SPNS253A May 2018 – September 2019 TMS570LC4357-EP
PRODUCTION DATA.
Table 5-26 and Table 5-27 list the access permissions for each bus master on the device. A bus master is a module that can initiate a read or a write transaction on the device.
Each slave module on either the CPU Interconnect Subsystem or the Peripheral Interconnect Subsystem is listed in Table 5-27. Allowed indicates that the module listed in the MASTERS column can access that slave module.
| MASTERS | SLAVES ON CPU INTERCONNECT SUBSYSTEM | ||||
|---|---|---|---|---|---|
| L2 Flash OTP, ECC, Bank 7 (EEPROM) | L2 FLASH | L2 SRAM | CACHE MEMORY | EMIF | |
| CPU Read | Allowed | Allowed | Allowed | Allowed | Allowed |
| CPU Write | Not allowed | Not allowed | Allowed | Allowed | Allowed |
| DMA PortA | Allowed | Allowed | Allowed | Not allowed | Allowed |
| POM | Not allowed | Not allowed | Allowed | Not allowed | Allowed |
| PS_SCR_M | Allowed | Allowed | Allowed | Not allowed | Allowed |
| ACP_M | Not allowed | Not Allowed | Allowed | Not allowed | Not allowed |
| MASTER ID TO PCRx | MASTERS | SLAVES ON PERIPHERAL INTERCONNECT SUBSYSTEM | |||
|---|---|---|---|---|---|
| CRC1/CRC2 | Resources Under
PCR2 and PCR3 |
Resources Under PCR1 | CPU Interconnect Subsystem SDC MMR Port (see Section 5.9.6) | ||
| 0 | CPU Read | Allowed | Allowed | Allowed | Allowed |
| CPU Write | Allowed | Allowed | Allowed | Allowed | |
| 1 | Reserved | – | – | – | – |
| 2 | DMA PortB | Allowed | Allowed | Allowed | Not allowed |
| 3 | HTU1 | Not allowed | Not allowed | Not allowed | Not allowed |
| 4 | HTU2 | Not allowed | Not allowed | Not allowed | Not allowed |
| 5 | FTU | Not allowed | Not allowed | Not allowed | Not allowed |
| 7 | DMM | Allowed | Allowed | Allowed | Allowed |
| 9 | DAP | Allowed | Allowed | Allowed | Allowed |
| 10 | EMAC | Not allowed | Allowed | Not allowed | Not allowed |