SPNS253A May 2018 – September 2019 TMS570LC4357-EP
PRODUCTION DATA.
| PARAMETER | MIN | MAX | UNIT | |
|---|---|---|---|---|
| ADREFHI | A-to-D high-voltage reference source | ADREFLO | VCCAD(1) | V |
| ADREFLO | A-to-D low-voltage reference source | VSSAD(1) | ADREFHI | V |
| VAI | Analog input voltage | ADREFLO | ADREFHI | V |
| IAIC | Analog input clamp current(2) (VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3) | –2 | 2 | mA |
| PARAMETER | DESCRIPTION/CONDITIONS | MIN | MAX | UNIT | ||
|---|---|---|---|---|---|---|
| Rmux | Analog input mux on-resistance | See Figure 6-10 | 250 | Ω | ||
| Rsamp | ADC sample switch on-resistance | See Figure 6-10 | 250 | Ω | ||
| Cmux | Input mux capacitance | See Figure 6-10 | 16 | pF | ||
| Csamp | ADC sample capacitance | See Figure 6-10 | 13 | pF | ||
| IAIL | Analog off-state input leakage current | VCCAD = 3.6 V | VSSAD ≤ VIN < VSSAD + 100 mV | –300 | 200 | nA |
| VSSAD + 100 mV ≤ VIN ≤ VCCAD – 200 mV | –280 | 280 | ||||
| VCCAD – 200 mV < VIN ≤ VCCAD | –200 | 650 | ||||
| IAIL | Analog off-state input leakage current | VCCAD = 5.25 V | VSSAD ≤ VIN < VSSAD + 300 mV | –1000 | 250 | nA |
| VSSAD + 300 mV ≤ VIN ≤ VCCAD – 300 mV | –450 | 450 | ||||
| VCCAD – 300 mV < VIN ≤ VCCAD | –250 | 2000 | ||||
| IAOSB(1) | Analog on-state input bias current | VCCAD = 3.6 V | VSSAD ≤ VIN < VSSAD + 100 mV | –10 | 2 | µA |
| VSSAD + 100 mV < VIN < VCCAD – 200 mV | –4 | 2 | ||||
| VCCAD – 200 mV < VIN < VCCAD | –4 | 16 | ||||
| IAOSB(1) | Analog on-state input bias current | VCCAD = 5.25 V | VSSAD ≤ VIN < VSSAD + 300 mV | –12 | 3 | µA |
| VSSAD + 300 mV ≤ VIN ≤ VCCAD – 300 mV | –5 | 3 | ||||
| VCCAD – 300 mV < VIN ≤ VCCAD | –5 | 18 | ||||
Figure 6-10 MibADC Input Equivalent Circuit | PARAMETER | MIN | NOM | MAX | UNIT | |
|---|---|---|---|---|---|
| tc(ADCLK)(1) | Cycle time, MibADC clock | 0.033 | µs | ||
| td(SH)(2) | Delay time, sample and hold time | 0.2 | µs | ||
| 12-BIT MODE | |||||
| td(C) | Delay time, conversion time | 0.4 | µs | ||
| td(SHC)(3) | Delay time, total sample/hold and conversion time | 0.6 | µs | ||
| 10-BIT MODE | |||||
| td(C) | Delay time, conversion time | 0.33 | µs | ||
| td(SHC)(3) | Delay time, total sample/hold and conversion time | 0.53 | µs | ||
| PARAMETER | DESCRIPTION/CONDITIONS | MIN | MAX | UNIT | ||
|---|---|---|---|---|---|---|
| CR | Conversion range over which specified accuracy is maintained | ADREFHI - ADREFLO | 3 | 3.6 | V | |
| ZSET | Zero Scale Offset | Difference between the first ideal transition (from code 000h to 001h) and the actual transition | 10-bit mode | 1 | LSB | |
| 12-bit mode | 2 | LSB | ||||
| FSET | Full Scale Offset | Difference between the range of the measured code transitions (from first to last) and the range of the ideal code transitions | 10-bit mode | 2 | LSB | |
| 12-bit mode | 3 | LSB | ||||
| EDNL | Differential nonlinearity error | Difference between the actual step width and the ideal value. (See Figure 6-11) | 10-bit mode | –1 | 1.5 | LSB |
| 12-bit mode | –1 | 2 | LSB | |||
| EINL | Integral nonlinearity error | Maximum deviation from the best straight line through the MibADC. MibADC transfer characteristics, excluding the quantization error. | 10-bit mode | –2 | 2 | LSB |
| 12-bit mode | –2 | 2 | LSB | |||
| ETOT | Total unadjusted error (after calibration) | Maximum value of the difference between an analog value and the ideal midstep value. | 10-bit mode | –2 | 2 | LSB |
| 12-bit mode | –4 | 4 | LSB | |||
| PARAMETER | DESCRIPTION/CONDITIONS | MIN | MAX | UNIT | ||
|---|---|---|---|---|---|---|
| CR | Conversion range over which specified accuracy is maintained | ADREFHI - ADREFLO | 3.6 | 5.25 | V | |
| ZSET | Zero Scale Offset | Difference between the first ideal transition (from code 000h to 001h) and the actual transition | 10-bit mode | 1 | LSB | |
| 12-bit mode | 2 | LSB | ||||
| FSET | Full Scale Offset | Difference between the range of the measured code transitions (from first to last) and the range of the ideal code transitions | 10-bit mode | 2 | LSB | |
| 12-bit mode | 3 | LSB | ||||
| EDNL | Differential nonlinearity error | Difference between the actual step width and the ideal value. (See Figure 6-11) | 10-bit mode | –1 | 1.5 | LSB |
| 12-bit mode | –1 | 3 | LSB | |||
| EINL | Integral nonlinearity error | Maximum deviation from the best straight line through the MibADC. MibADC transfer characteristics, excluding the quantization error. | 10-bit mode | –2 | 2 | LSB |
| 12-bit mode | –4.5 | 2 | LSB | |||
| ETOT | Total unadjusted error (after calibration) | Maximum value of the difference between an analog value and the ideal midstep value. | 10-bit mode | –2 | 2 | LSB |
| 12-bit mode | –6 | 5 | LSB | |||