SPNS253A May 2018 – September 2019 TMS570LC4357-EP
PRODUCTION DATA.
| MODULES | VIM INTERRUPT SOURCES | DEFAULT VIM
INTERRUPT CHANNEL |
|---|---|---|
| ESM | ESM high-level interrupt (NMI) | 0 |
| Reserved | Reserved | 1 |
| RTI | RTI1 compare interrupt 0 | 2 |
| RTI | RTI1 compare interrupt 1 | 3 |
| RTI | RTI1 compare interrupt 2 | 4 |
| RTI | RTI1 compare interrupt 3 | 5 |
| RTI | RTI1 overflow interrupt 0 | 6 |
| RTI | RTI1 overflow interrupt 1 | 7 |
| RTI | RTI1 time-base | 8 |
| GIO | GIO high level interrupt | 9 |
| NHET1 | NHET1 high-level interrupt (priority level 1) | 10 |
| HET TU1 | HET TU1 level 0 interrupt | 11 |
| MIBSPI1 | MIBSPI1 level 0 interrupt | 12 |
| LIN1 | LIN1 level 0 interrupt | 13 |
| MIBADC1 | MIBADC1 event group interrupt | 14 |
| MIBADC1 | MIBADC1 software group 1 interrupt | 15 |
| DCAN1 | DCAN1 level 0 interrupt | 16 |
| MIBSPI2 | MIBSPI2 level 0 interrupt | 17 |
| FlexRay | FlexRay level 0 interrupt (CC_int0) | 18 |
| CRC1 | CRC1 Interrupt | 19 |
| ESM | ESM low-level interrupt | 20 |
| SYSTEM | Software interrupt for Cortex-R5F (SSI) | 21 |
| CPU | Cortex-R5F PMU Interrupt | 22 |
| GIO | GIO low level interrupt | 23 |
| NHET1 | NHET1 low level interrupt (priority level 2) | 24 |
| HET TU1 | HET TU1 level 1 interrupt | 25 |
| MIBSPI1 | MIBSPI1 level 1 interrupt | 26 |
| LIN1 | LIN1 level 1 interrupt | 27 |
| MIBADC1 | MIBADC1 software group 2 interrupt | 28 |
| DCAN1 | DCAN1 level 1 interrupt | 29 |
| MIBSPI2 | MIBSPI2 level 1 interrupt | 30 |
| MIBADC1 | MIBADC1 magnitude compare interrupt | 31 |
| FlexRay | FlexRay level 1 interrupt (CC_int1) | 32 |
| DMA | FTCA interrupt | 33 |
| DMA | LFSA interrupt | 34 |
| DCAN2 | DCAN2 level 0 interrupt | 35 |
| DMM | DMM level 0 interrupt | 36 |
| MIBSPI3 | MIBSPI3 level 0 interrupt | 37 |
| MIBSPI3 | MIBSPI3 level 1 interrupt | 38 |
| DMA | HBCA interrupt | 39 |
| DMA | BTCA interrupt | 40 |
| EMIF | AEMIFINT | 41 |
| DCAN2 | DCAN2 level 1 interrupt | 42 |
| DMM | DMM level 1 interrupt | 43 |
| DCAN1 | DCAN1 IF3 interrupt | 44 |
| DCAN3 | DCAN3 level 0 interrupt | 45 |
| DCAN2 | DCAN2 IF3 interrupt | 46 |
| FPU | FPU interrupt of Cortex-R5F | 47 |
| FlexRay TU | FlexRay TU Transfer Status interrupt (TU_Int0) | 48 |
| MIBSPI4 | MIBSPI4 level 0 interrupt | 49 |
| MIBADC2 | MibADC2 event group interrupt | 50 |
| MIBADC2 | MibADC2 software group1 interrupt | 51 |
| FlexRay | FlexRay T0C interrupt (CC_tint0) | 52 |
| MIBSPI5 | MIBSPI5 level 0 interrupt | 53 |
| MIBSPI4 | MIBSPI4 level 1 interrupt | 54 |
| DCAN3 | DCAN3 level 1 interrupt | 55 |
| MIBSPI5 | MIBSPI5 level 1 interrupt | 56 |
| MIBADC2 | MibADC2 software group2 interrupt | 57 |
| FlexRay TU | FlexRay TU Error interrupt (TU_Int1) | 58 |
| MIBADC2 | MibADC2 magnitude compare interrupt | 59 |
| DCAN3 | DCAN3 IF3 interrupt | 60 |
| L2FMC | FSM_DONE interrupt | 61 |
| FlexRay | FlexRay T1C interrupt (CC_tint1) | 62 |
| NHET2 | NHET2 level 0 interrupt | 63 |
| SCI3 | SCI3 level 0 interrupt | 64 |
| NHET TU2 | NHET TU2 level 0 interrupt | 65 |
| I2C1 | I2C level 0 interrupt | 66 |
| Reserved | Reserved | 67–72 |
| NHET2 | NHET2 level 1 interrupt | 73 |
| SCI3 | SCI3 level 1 interrupt | 74 |
| NHET TU2 | NHET TU2 level 1 interrupt | 75 |
| Ethernet | C0_MISC_PULSE | 76 |
| Ethernet | C0_TX_PULSE | 77 |
| Ethernet | C0_THRESH_PULSE | 78 |
| Ethernet | C0_RX_PULSE | 79 |
| HWAG1 | HWA_INT_REQ_H | 80 |
| HWAG2 | HWA_INT_REQ_H | 81 |
| DCC1 | DCC1 done interrupt | 82 |
| DCC2 | DCC2 done interrupt | 83 |
| SYSTEM | Reserved | 84 |
| PBIST | PBIST Done | 85 |
| Reserved | Reserved | 86–87 |
| HWAG1 | HWA_INT_REQ_L | 88 |
| HWAG2 | HWA_INT_REQ_L | 89 |
| ePWM1INTn | ePWM1 Interrupt | 90 |
| ePWM1TZINTn | ePWM1 Trip Zone Interrupt | 91 |
| ePWM2INTn | ePWM2 Interrupt | 92 |
| ePWM2TZINTn | ePWM2 Trip Zone Interrupt | 93 |
| ePWM3INTn | ePWM3 Interrupt | 94 |
| ePWM3TZINTn | ePWM3 Trip Zone Interrupt | 95 |
| ePWM4INTn | ePWM4 Interrupt | 96 |
| ePWM4TZINTn | ePWM4 Trip Zone Interrupt | 97 |
| ePWM5INTn | ePWM5 Interrupt | 98 |
| ePWM5TZINTn | ePWM5 Trip Zone Interrupt | 99 |
| ePWM6INTn | ePWM6 Interrupt | 100 |
| ePWM6TZINTn | ePWM6 Trip Zone Interrupt | 101 |
| ePWM7INTn | ePWM7 Interrupt | 102 |
| ePWM7TZINTn | ePWM7 Trip Zone Interrupt | 103 |
| eCAP1INTn | eCAP1 Interrupt | 104 |
| eCAP2INTn | eCAP2 Interrupt | 105 |
| eCAP3INTn | eCAP3 Interrupt | 106 |
| eCAP4INTn | eCAP4 Interrupt | 107 |
| eCAP5INTn | eCAP5 Interrupt | 108 |
| eCAP6INTn | eCAP6 Interrupt | 109 |
| eQEP1INTn | eQEP1 Interrupt | 110 |
| eQEP2INTn | eQEP2 Interrupt | 111 |
| Reserved | Reserved | 112 |
| DCAN4 | DCAN4 Level 0 interrupt | 113 |
| I2C2 | I2C2 interrupt | 114 |
| LIN2 | LIN2 level 0 interrupt | 115 |
| SCI4 | SCI4 level 0 interrupt | 116 |
| DCAN4 | DCAN4 Level 1 interrupt | 117 |
| LIN2 | LIN2 level 1 interrupt | 118 |
| SCI4 | SCI4 level 1 interrupt | 119 |
| DCAN4 | DCAN4 IF3 Interrupt | 120 |
| CRC2 | CRC2 Interrupt | 121 |
| Reserved | Reserved | 122 |
| Reserved | Reserved | 123 |
| EPC | EPC FIFO FULL or CAM FULL interrupt | 124 |
| Reserved | Reserved | 125-127 |
NOTE
Address location 0x00000000 in the VIM RAM is reserved for the phantom interrupt ISR entry; therefore only request channels 0..126 can be used and are offset by one address in the VIM RAM.
NOTE
The EMIF_nWAIT signal has a pull-up on it. The EMIF module generates a "Wait Rise" interrupt whenever it detects a rising edge on the EMIF_nWAIT signal. This interrupt condition is indicated as soon as the device is powered up. This can be ignored if the EMIF_nWAIT signal is not used in the application. If the EMIF_nWAIT signal is actually used in the application, then the external slave memory must always drive the EMIF_nWAIT signal such that an interrupt is not caused due to the default pull-up on this signal.
NOTE
The lower-order interrupt channels are higher priority channels than the higher-order interrupt channels.
NOTE
The application can change the mapping of interrupt sources to the interrupt channels through the interrupt channel control registers (CHANCTRLx) inside the VIM module.