5.6.4 Clock Test Mode
The TMS570 platform architecture defines a special mode that allows various clock signals to be selected and output on the ECLK1 terminal and N2HET1[12] device outputs. This special mode, Clock Test Mode, is very useful for debugging purposes and can be configured through the CLKTEST register in the system module. See Table 5-18 and Table 5-19 for the CLKTEST bits value and signal selection.
Table 5-18 Clock Test Mode Options for Signals on ECLK1
| SEL_ECP_PIN = CLKTEST[4-0] |
SIGNAL ON ECLK1 |
| 00000 |
Oscillator Clock |
| 00001 |
PLL1 Clock Output |
| 00010 |
Reserved |
| 00011 |
EXTCLKIN1 |
| 00100 |
Low-Frequency Low-Power Oscillator (LFLPO) Clock [CLK80K] |
| 00101 |
High-Frequency Low-Power Oscillator (HFLPO) Clock [CLK10M] |
| 00110 |
PLL2 Clock Output |
| 00111 |
EXTCLKIN2 |
| 01000 |
GCLK1 |
| 01001 |
RTI1 Base |
| 01010 |
Reserved |
| 01011 |
VCLKA1 |
| 01100 |
VCLKA2 |
| 01101 |
Reserved |
| 01110 |
VCLKA4_DIVR |
| 01111 |
Flash HD Pump Oscillator |
| 10000 |
Reserved |
| 10001 |
HCLK |
| 10010 |
VCLK |
| 10011 |
VCLK2 |
| 10100 |
VCLK3 |
| 10101 |
Reserved |
| 10110 |
Reserved |
| 10111 |
EMAC Clock Output |
| 11000 |
Reserved |
| 11001 |
Reserved |
| 11010 |
Reserved |
| 11011 |
Reserved |
| 11100 |
Reserved |
| 11101 |
Reserved |
| 11110 |
Reserved |
| 11111 |
Reserved |
Table 5-19 Clock Test Mode Options for Signals on N2HET1[12]
| SEL_GIO_PIN = CLKTEST[11-8] |
SIGNAL ON N2HET1[12] |
| 0000 |
Oscillator Valid Status |
| 0001 |
PLL1 Valid Status |
| 0010 |
Reserved |
| 0011 |
Reserved |
| 0100 |
Reserved |
| 0101 |
HFLPO Clock Output Valid Status [CLK10M] |
| 0110 |
PLL2 Valid Status |
| 0111 |
Reserved |
| 1000 |
LFLPO Clock Output Valid Status [CLK80K] |
| 1001 |
Oscillator Valid status |
| 1010 |
Oscillator Valid status |
| 1011 |
Oscillator Valid status |
| 1100 |
Oscillator Valid status |
| 1101 |
Reserved |
| 1110 |
VCLKA4 |
| 1111 |
Oscillator Valid status |