ZHCSJK5D January 2018 – June 2022 TCAN4550-Q1
PRODUCTION DATA
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| DMS[1:0] | RSVD | RF1L | F1F | ||||
| R | R | R | R | ||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RSVD | F1PI[5:0] | ||||||
| R | R | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RSVD | F1GI[5:0] | ||||||
| R | R | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD | F1FL[6:0] | ||||||
| R | R | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:30 | DMS[1:0] | R | 0x0 | Debug Message Status 00 - Idle state, wait for reception of debug messages, DMA request is cleared 01 - Debug message A received 10 - Debug messages A, B received 11 - Debug messages A, B, C received, DMA request is set |
| 29:26 | RSVD | R | 0x0 | Reserved |
| 25 | RF1L | R | 0 | Rx FIFO 1 Message Lost This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset 0 - No Rx FIFO 1 message lost 1 - Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero Note: Overwriting the oldest message when RXF1C.F1OM = ‘1’ will not set this flag. |
| 24 | F1F | R | 0 | Rx FIFO 1 Full 0 - Rx FIFO 1 not full 1 - Rx FIFO 1 full |
| 23:22 | RSVD | R | 0x0 | Reserved |
| 21:16 | F1PI[5:0] | R | 0x0 | Rx FIFO 1 Put Index Rx FIFO 1 write index pointer, range 0 to 63 |
| 15:14 | RSVD | R | 0x0 | Reserved |
| 13:8 | F1GI[5:0] | R | 0x0 | Rx FIFO 1 Get Index Rx FIFO 1 read index pointer, range 0 to 63. |
| 7 | RSVD | R | 0 | Reserved |
| 6:0 | F1FL[6:0] | R | 0x0 | Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1, range 0 to 64. |