ZHCSJK5D January 2018 – June 2022 TCAN4550-Q1
PRODUCTION DATA
The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signaled on an interrupt line.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RSVD | ARAE | PEDE | PEAE | WDIE | BOE | EWE | |
| R | R/W | R/W | R/W | R/W | R/W | R/W | |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| EPE | ELOE | BEUE | BECE | DRXE | TOOE | MRAFE | TSWE |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TEFLE | TEFFE | TEFW | TEFNE | TFEE | TCFE | TCE | HPME |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RF1LE | RF1FE | RF1WE | RF1NE | RF0LE | RF0FE | RF0WE | RF0NE |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:30 | RSVD | R | 0x0 | Reserved |
| 29 | ARAE | R/W | 0 | Access to Reserved Address Enable |
| 28 | PEDE | R/W | 0 | Protocol Error in Data Phase Enable |
| 27 | PEAE | R/W | 0 | Protocol Error in Arbitration Phase Enable |
| 26 | WDIE | R/W | 0 | Watchdog Interrupt Enable |
| 25 | BOE | R/W | 0 | Bus_Off Status Interrupt Enable |
| 24 | EWE | R/W | 0 | Warning Status Interrupt Enable |
| 23 | EPE | R/W | 0 | Error Passive Interrupt Enable |
| 22 | ELOE | R/W | 0 | Error Logging Overflow Interrupt Enable |
| 21 | BEUE | R/W | 0 | Bit Error Uncorrected Interrupt Enable |
| 20 | BECE | R/W | 0 | Bit Error Corrected Interrupt Enable |
| 19 | DRXE | R/W | 0 | Message stored to Dedicated Rx Buffer Interrupt Enable |
| 18 | TOOE | R/W | 0 | Timeout Occurred Interrupt Enable |
| 17 | MRAFE | R/W | 0 | Message RAM Access Failure Interrupt Enable |
| 16 | TSWE | R/W | 0 | Timestamp Wraparound Interrupt Enable |
| 15 | TEFLE | R/W | 0 | Tx Event FIFO Event Lost Interrupt Enable |
| 14 | TEFFE | R/W | 0 | Tx Event FIFO Full Interrupt Enable |
| 13 | TEFW | R/W | 0 | Tx Event FIFO Watermark Reached Interrupt Enable |
| 12 | TEFNE | R/W | 0 | Tx Event FIFO New Entry Interrupt Enable |
| 11 | TFEE | R/W | 0 | Tx FIFO Empty Interrupt Enable |
| 10 | TCFE | R/W | 0 | Transmission Cancellation Finished Interrupt Enable |
| 9 | TCE | R/W | 0 | Transmission Completed Interrupt Enable |
| 8 | HPME | R/W | 0 | High Priority Message Interrupt Enable |
| 7 | RF1LE | R/W | 0 | Rx FIFO 1 Message Lost Interrupt Enable |
| 6 | RF1FE | R/W | 0 | Rx FIFO 1 Full Interrupt Enable |
| 5 | RF1WE | R/W | 0 | Rx FIFO 1 Watermark Reached Interrupt Enable |
| 4 | RF1NE | R/W | 0 | Rx FIFO 1 New Message Interrupt Enable |
| 3 | RF0LE | R/W | 0 | Rx FIFO 0 Message Lost Interrupt Enable |
| 2 | RF0FE | R/W | 0 | Rx FIFO 0 Full Interrupt Enable |
| 1 | RF0WE | R/W | 0 | Rx FIFO 0 Watermark Reached Interrupt Enable |
| 0 | RF0NE | R/W | 0 | Rx FIFO 0 New Message Interrupt Enable |