ZHCSJK5D January 2018 – June 2022 TCAN4550-Q1
PRODUCTION DATA
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| ND31 | ND30 | ND29 | ND28 | ND27 | ND26 | ND25 | ND24 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| ND23 | ND22 | ND21 | ND20 | ND19 | ND18 | ND17 | ND16 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ND15 | ND14 | ND13 | ND12 | ND11 | ND10 | ND9 | ND8 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ND7 | ND6 | ND5 | ND4 | ND3 | ND2 | ND1 | ND1 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | ND31 to ND0 | R/W | 0 | The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. 0 - Rx Buffer not updated 1 - Rx Buffer updated from new message |